MANAGING CLOCK TRIGGER SIGNALS FOR ASYNCHRONOUS CLOCK DOMAINS

    公开(公告)号:US20240310868A1

    公开(公告)日:2024-09-19

    申请号:US18398496

    申请日:2023-12-28

    CPC classification number: G06F1/06 G06F1/08

    Abstract: Embodiments disclosed herein relate to managing clock signals across clock domains. In one implementation, a system is configured to derive a base clock signal from a first clock trigger signal produced by a first subsystem in a first clock domain of the clocking system. The system is further configured to generate a second clock trigger signal based on the base clock signal and a main clock of a second subsystem in a second clock domain of the clocking system. The system is also configured to supply the second clock trigger signal to a second peripheral in the second clock domain.

    DEVICE TRIMMING VIA DIRECT MEMORY ACCESS

    公开(公告)号:US20240385924A1

    公开(公告)日:2024-11-21

    申请号:US18345449

    申请日:2023-06-30

    Abstract: Various examples disclosed herein relate to trimming of system elements to prepare the elements for execution of boot code and application code. In an example embodiment, a system is provided. The system includes system control circuitry, direct memory access (DMA) circuitry, and processing circuitry. The system control circuitry is configured to instruct the DMA circuitry to obtain trim data from memory upon detecting that a first group of system elements has reached an initialized state. The DMA circuitry obtains the trim data and writes it to trim registers. The system control circuitry supplies the trim data to a second group of system elements to bring them to an operational level, then instructs the processing circuitry to execute boot code.

    DEVICE TRIMMING VIA DIRECT MEMORY ACCESS

    公开(公告)号:US20250094276A1

    公开(公告)日:2025-03-20

    申请号:US18964844

    申请日:2024-12-02

    Abstract: Various examples disclosed herein relate to trimming of system elements to prepare the elements for execution of boot code and application code. In an example embodiment, a system is provided. The system includes system control circuitry, direct memory access (DMA) circuitry, and processing circuitry. The system control circuitry is configured to instruct the DMA circuitry to obtain trim data from memory upon detecting that a first group of system elements has reached an initialized state. The DMA circuitry obtains the trim data and writes it to trim registers. The system control circuitry supplies the trim data to a second group of system elements to bring them to an operational level, then instructs the processing circuitry to execute boot code.

    DYNAMIC CONTROL OF A MULTI-TRIM OSCILLATOR
    4.
    发明公开

    公开(公告)号:US20240313749A1

    公开(公告)日:2024-09-19

    申请号:US18390818

    申请日:2023-12-20

    CPC classification number: H03K5/00006 H03K3/037 H03K5/133 H03K21/10

    Abstract: Embodiments disclosed herein relate to the management of a multi-trim oscillator to provide synchronization across multiple frequencies derived from the multi-trim oscillator without causing spurious pulses of clock output. In one example, a system provides a first clock signal via an oscillator and a second clock signal based on the first clock signal and a divider. The system further receives a first signal that indicates a change in a frequency of the first clock signal from a first frequency to a second frequency. In response to the first signal, the system determines an edge of the second clock signal and provides, at a time based on the edge of the second clock signal, a second signal to the oscillator to cause the change to the second frequency.

    FSM based clock switching of asynchronous clocks

    公开(公告)号:US12174659B2

    公开(公告)日:2024-12-24

    申请号:US17824695

    申请日:2022-05-25

    Abstract: Aspects of the disclosure provide for an apparatus. In an example, the apparatus includes a clock switching circuit coupled to oscillators and one or more circuit units. The clock switching circuit is configured to receive, from the oscillators, a set of frequency signals, provide an uplink primary clock signal and an enable signal to the one or more circuit units, the enable signal determined synchronously with the uplink primary clock signal, receive, from the one or more circuit units or a clock management circuit, a clock frequency request, provide the uplink primary clock signal based on a first signal of the set of frequency signals, and according to the clock frequency request, determining whether to continue to provide the uplink primary clock signal based on the first signal or on a second signal of the set of frequency signals.

    Device trimming via direct memory access

    公开(公告)号:US12158804B1

    公开(公告)日:2024-12-03

    申请号:US18345449

    申请日:2023-06-30

    Abstract: Various examples disclosed herein relate to trimming of system elements to prepare the elements for execution of boot code and application code. In an example embodiment, a system is provided. The system includes system control circuitry, direct memory access (DMA) circuitry, and processing circuitry. The system control circuitry is configured to instruct the DMA circuitry to obtain trim data from memory upon detecting that a first group of system elements has reached an initialized state. The DMA circuitry obtains the trim data and writes it to trim registers. The system control circuitry supplies the trim data to a second group of system elements to bring them to an operational level, then instructs the processing circuitry to execute boot code.

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