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    METHODS AND APPARATUS TO CONFIGURE AN INTEGRATED CIRCUIT USING A DIRECT MEMORY ACCESS CONTROLLER
    1.
    发明公开
    METHODS AND APPARATUS TO CONFIGURE AN INTEGRATED CIRCUIT USING A DIRECT MEMORY ACCESS CONTROLLER 审中-公开

    公开(公告)号：US20230315661A1

    公开(公告)日：2023-10-05

    申请号：US18129665

    申请日：2023-03-31

    申请人： Texas Instruments Incorporated

    发明人： Michael Zwerg

    IPC分类号： G06F13/28 ,  G06F13/16 ,  G06F12/02

    CPC分类号： G06F13/28 ,  G06F13/1673 ,  G06F12/0238

    摘要： An example apparatus includes a first memory configured to store a table, and a direct memory access controller coupled to the first memory and including a second memory local to the direct memory access controller, the direct memory access controller configured to read a first set of data from a first location in the table, wherein the first set of data includes an address, write the first set of data from the table to the second memory of the direct memory access controller, read a second set of data from a second location in the table, the second location different than the first location, and write the second set of data to a third location in the first memory, wherein the third location corresponds to the address of the first set of data.

    METHODS AND APPARATUS TO FACILITATE SAFE STARTUP OF A POWER MANAGEMENT UNIT
    2.
    发明公开
    METHODS AND APPARATUS TO FACILITATE SAFE STARTUP OF A POWER MANAGEMENT UNIT 审中-公开

    公开(公告)号：US20230315142A1

    公开(公告)日：2023-10-05

    申请号：US18129674

    申请日：2023-03-31

    申请人： Texas Instruments Incorporated

    发明人： Michael Zwerg

    IPC分类号： G06F1/08 ,  G06F1/10

    CPC分类号： G06F1/08 ,  G06F1/10

    摘要： An example apparatus includes an input terminal; an output terminal; a delay circuit including an input terminal and an output terminal, the input terminal coupled of the delay circuit coupled to the input terminal; a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a supply voltage terminal, the second input terminal of the comparator coupled to a reference voltage terminal; and a logic AND gate including a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the logic AND gate coupled to the output terminal of the comparator, the second input terminal of the logic AND gate coupled to the output terminal of the delay circuit, the third input terminal of the logic AND gate coupled to the input terminal, and the output terminal of the logic AND gate coupled to the output terminal.

    COMPUTE THROUGH POWER LOSS HARDWARE APPROACH FOR PROCESSING DEVICE HAVING NONVOLATILE LOGIC MEMORY
    3.
    发明申请
    COMPUTE THROUGH POWER LOSS HARDWARE APPROACH FOR PROCESSING DEVICE HAVING NONVOLATILE LOGIC MEMORY 有权

    公开(公告)号：US20210373647A1

    公开(公告)日：2021-12-02

    申请号：US17404125

    申请日：2021-08-17

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Michael Zwerg ,  Steven Craig Bartling ,  Sudhanshu Khanna

    IPC分类号： G06F1/3293 ,  G06F3/06 ,  G06F1/3206 ,  G06F1/3287 ,  G06F11/07

    摘要： A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

    PROCESSOR EVENT MANAGER
    4.
    发明公开
    PROCESSOR EVENT MANAGER 审中-公开

    公开(公告)号：US20240281394A1

    公开(公告)日：2024-08-22

    申请号：US18458369

    申请日：2023-08-30

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Michael Zwerg

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： Various embodiments disclosed herein relate to an event manager for handling event notification and acknowledgement between circuits in a computing device. The event manager may be configured with static channels, direct memory access (DMA) channels, and dynamically configured channels. Each of the channels has conductors that allow a publishing circuit to assert a request signal on a conductor to notify the subscribing circuit of an event and the subscribing circuit to assert an acknowledge signal on a second conductor to notify the publishing circuit of receipt of the request signal. Using the request and acknowledge signals, the publishing circuit and subscribing circuit can engage in a 4-way handshake that ensures no events are lost and the events can be communicated reliably across clock domains.

    Compute through power loss hardware approach for processing device having nonvolatile logic memory
    5.
    发明授权
    Compute through power loss hardware approach for processing device having nonvolatile logic memory 有权

    公开(公告)号：US11132050B2

    公开(公告)日：2021-09-28

    申请号：US16451260

    申请日：2019-06-25

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Michael Zwerg ,  Steven Craig Bartling ,  Sudhanshu Khanna

    IPC分类号： G06F1/3293 ,  G06F3/06 ,  G06F1/3206 ,  G06F1/3287 ,  G06F11/07

    摘要： A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

    Compute through power loss hardware approach for processing device having nonvolatile logic memory
    8.
    发明授权
    Compute through power loss hardware approach for processing device having nonvolatile logic memory 有权

    公开(公告)号：US10331203B2

    公开(公告)日：2019-06-25

    申请号：US15016449

    申请日：2016-02-05

    申请人： Texas Instruments Incorporated

    发明人： Michael Zwerg ,  Steven Craig Bartling ,  Sudhanshu Khanna

    IPC分类号： G06F1/3293 ,  G06F1/3287 ,  G06F3/06 ,  G06F11/07 ,  G06F1/3206

    摘要： A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.