公开(公告)号：US10249607B1

公开(公告)日：2019-04-02

申请号：US15844035

申请日：2017-12-15

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Akram Ali Salman

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8249 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/732

Abstract: An integrated circuit includes a stacked NPN having an upper NPN connected to a lower NPN. The upper NPN includes an upper collector, an upper base, and an upper emitter. The lower NPN includes a lower collector, a lower base, and a lower emitter. The upper collector includes collector segments on opposite sides of the lower emitter. The collector segments are laterally separated by collector separators which are aligned to orientation directions in the collector segments. The upper collector does not have collector separators across the orientation directions.

公开(公告)号：US11521961B2

公开(公告)日：2022-12-06

申请号：US16914579

申请日：2020-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Akram Ali Salman ,  Guruvayurappan Mathur ,  Ryo Tsukahara

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/73

Abstract: An integrated circuit includes a bipolar transistor, e.g. a back-ballasted NPN, that can conduct laterally and vertically. At a low voltage breakdown and low current conduction occur laterally near a substrate surface, while at a higher voltage vertical conduction occurs in a more highly-doped channel below the surface. A relatively high-resistance region at the surface has a low doping level to guide the conduction deeper into the collector.

公开(公告)号：US20200328204A1

公开(公告)日：2020-10-15

申请号：US16914579

申请日：2020-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Akram Ali Salman ,  Guruvayurappan Mathur ,  Ryo Tsukahara

IPC: H01L27/02 ,  H01L29/73 ,  H01L29/66 ,  H01L27/06 ,  H01L29/08 ,  H01L29/06

Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.

公开(公告)号：US11869986B2

公开(公告)日：2024-01-09

申请号：US17459991

申请日：2021-08-27

Applicant: Texas Instruments Incorporated

Inventor： Umamaheswari Aghoram ,  Akram Ali Salman ,  Binghua Hu ,  Alexei Sadovnikov

IPC: H01L29/866 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L29/866 ,  H01L27/0255 ,  H01L29/66106 ,  H01L27/0259

Abstract: A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.

公开(公告)号：US20210005599A1

公开(公告)日：2021-01-07

申请号：US17028001

申请日：2020-09-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Akram Ali Salman

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8249 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/732 ,  H01L27/082

Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.

公开(公告)号：US20240088305A1

公开(公告)日：2024-03-14

申请号：US18514413

申请日：2023-11-20

Applicant: Texas Instruments Incorporated

Inventor： Umamaheswari Aghoram ,  Akram Ali Salman ,  Binghua Hu ,  Alexei Sadovnikov

IPC: H01L29/866 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L29/866 ,  H01L27/0255 ,  H01L29/66106 ,  H01L27/0259

Abstract: A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.

公开(公告)号：US20230066563A1

公开(公告)日：2023-03-02

申请号：US17459991

申请日：2021-08-27

Applicant: Texas Instruments Incorporated

Inventor： Umamaheswari Aghoram ,  Akram Ali Salman ,  Binghua Hu ,  Alexei Sadovnikov

IPC: H01L29/866 ,  H01L27/02 ,  H01L29/66

Abstract: A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.

公开(公告)号：US20190229111A1

公开(公告)日：2019-07-25

申请号：US16371960

申请日：2019-04-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Akram Ali Salman

IPC: H01L27/02 ,  H01L29/732 ,  H01L29/06 ,  H01L29/08 ,  H01L23/528 ,  H01L29/10 ,  H01L21/8249 ,  H01L29/66

Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.

公开(公告)号：US20190181134A1

公开(公告)日：2019-06-13

申请号：US15838876

申请日：2017-12-12

Applicant: Texas Instruments Incorporated

Inventor： Akram Ali Salman ,  Guruvayurappan Mathur ,  Ryo Tsukahara

IPC: H01L27/02 ,  H01L29/73 ,  H01L29/08 ,  H01L27/06 ,  H01L29/66

CPC classification number: H01L27/0262 ,  H01L27/0259 ,  H01L27/0623 ,  H01L29/0646 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/66234 ,  H01L29/66287 ,  H01L29/7302 ,  H01L29/7304

Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.

公开(公告)号：US20210408270A1

公开(公告)日：2021-12-30

申请号：US17357142

申请日：2021-06-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Zaichen Chen ,  Akram Ali Salman

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: An integrated circuit includes a semiconductor substrate having a doped region, e.g. a DWELL, with a first conductivity type. A source region is located within the doped region, the source region having a second opposite conductivity type. A drain region having the second conductivity type is spaced apart from the source region. A gate electrode is located between the source region and the drain region, the gate electrode partially overlapping the doped region. A body region having the first conductivity type is located within the doped region. A dielectric layer forms a closed path around the body region.