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公开(公告)号：US11901393B2
公开(公告)日：2024-02-13
申请号：US17184965
申请日：2021-02-25
发明人： Jhy-Jyi Sze , Sin-Yi Jiang , Yi-Shin Chu , Yin-Kai Liao , Hsiang-Lin Chen , Kuan-Chieh Huang , Jung-I Lin
IPC分类号： H01L27/146 , G01S7/481
CPC分类号： H01L27/14649 , H01L27/1463 , H01L27/14623 , H01L27/14625 , H01L27/14636 , H01L27/14689 , H01L27/14698 , G01S7/4816
摘要： The present disclosure provides a semiconductor structure, including a substrate including a first material, wherein the first material generates electrical signals from radiation within a first range of wavelengths, an image sensor element including a second material, wherein the second material generates electrical signals from radiation within a second range of wavelengths, the second range is different from first range, a transparent layer proximal to a light receiving surface of the image sensor element, wherein the transparent layer is transparent to radiation within the second range of wavelength, and an interconnect structure connected to a signal transmitting surface of the image sensor element.
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公开(公告)号：US20230361005A1
公开(公告)日：2023-11-09
申请号：US18355463
申请日：2023-07-20
发明人： Min-Feng Kao , Dun-Nian Yaung , Hsing-Chih Lin , Jen-Cheng Liu , Yi-Shin Chu , Ping-Tzu Chen
IPC分类号： H01L23/48 , H01L25/065 , H01L23/00 , H01L21/768 , H01L25/00
CPC分类号： H01L23/481 , H01L25/0657 , H01L24/08 , H01L21/76898 , H01L24/80 , H01L25/50 , H01L2224/80896 , H01L2225/06524 , H01L2225/06544 , H01L2224/08145 , H01L2224/80895
摘要： The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed within a dielectric structure on a substrate, and a second via disposed within the dielectric structure and laterally separated from the first via by the dielectric structure. The first via has a first width that is smaller than a second width of the second via. An interconnect wire vertically contacts the second via and extends laterally past an outermost sidewall of the second via. A through-substrate via (TSV) is arranged over the second via and extends through the substrate. The TSV has a minimum width that is smaller than the second width of the second via. The second via has opposing outermost sidewalls that are laterally outside of the TSV.
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3.发明申请公开(公告)号：US20220302336A1
公开(公告)日：2022-09-22
申请号：US17383687
申请日：2021-07-23
发明人： Jhy-Jyi Sze , Sin-Yi Jiang , Yi-Shin Chu , Yin-Kai Liao , Hsiang-Lin Chen , Kuan-Chieh Huang
IPC分类号： H01L31/112 , H01L31/18
摘要： Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed in a silicon substrate, in some embodiments, or on a silicon substrate, in some embodiments. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair doped region pair in the germanium layer is configured as an e-lens of the germanium-based sensor.
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公开(公告)号：US11437708B2
公开(公告)日：2022-09-06
申请号：US17149853
申请日：2021-01-15
发明人： Po-Hsiang Huang , Fong-Yuan Chang , Tsui-Ping Wang , Yi-Shin Chu
摘要： A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.
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公开(公告)号：US11387167B2
公开(公告)日：2022-07-12
申请号：US16920430
申请日：2020-07-03
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Ching-Chun Wang , Kuan-Chieh Huang , Hsing-Chih Lin , Yi-Shin Chu
IPC分类号： H01L23/52 , H01L23/48 , H01L21/48 , H01L21/02 , H01L23/522 , H01L21/768
摘要： Present disclosure provides a semiconductor structure, including a semiconductor substrate, a first metal layer, and a through substrate via (TSV). The semiconductor substrate has an active side. The first metal layer is closest to the active side of the semiconductor substrate, and the first metal layer has a first continuous metal feature. The TSV is extending from the semiconductor substrate to the first continuous metal feature. A width of the TSV at the first metal layer is wider than a width of the first continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.
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公开(公告)号：US20190013345A1
公开(公告)日：2019-01-10
申请号：US16113819
申请日：2018-08-27
发明人： Meng-Hsun Wan , Yi-Shin Chu , Szu-Ying Chen , Pao-Tung Chen , Jen-Cheng Liu , Dun-Nian Yaung
IPC分类号： H01L27/146 , H04N5/378 , H01L31/0376 , H01L31/0352 , H01L31/0224 , H01L31/18
CPC分类号： H01L27/14632 , H01L27/14621 , H01L27/14627 , H01L27/1463 , H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/14645 , H01L27/14685 , H01L27/14687 , H01L27/14689 , H01L27/1469 , H01L31/022466 , H01L31/035218 , H01L31/03762 , H01L31/18 , H04N5/378
摘要： A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode.
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公开(公告)号：US11908900B2
公开(公告)日：2024-02-20
申请号：US17869885
申请日：2022-07-21
发明人： Yin-Kai Liao , Sin-Yi Jiang , Hsiang-Lin Chen , Yi-Shin Chu , Po-Chun Liu , Kuan-Chieh Huang , Jyh-Ming Hung , Jen-Cheng Liu
IPC分类号： H01L29/10 , H01L29/167 , H01L29/49 , H01L29/66
CPC分类号： H01L29/1087 , H01L29/167 , H01L29/4933 , H01L29/6659
摘要： The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
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8.发明授权公开(公告)号：US11855237B2
公开(公告)日：2023-12-26
申请号：US18151828
申请日：2023-01-09
发明人： Jhy-Jyi Sze , Sin-Yi Jiang , Yi-Shin Chu , Yin-Kai Liao , Hsiang-Lin Chen , Kuan-Chieh Huang
IPC分类号： H01L31/112 , H01L31/18 , H01L27/146 , H01L29/808 , H01L29/10 , H01L29/66
CPC分类号： H01L31/1129 , H01L27/14679 , H01L29/66893 , H01L29/808 , H01L31/112 , H01L31/1804 , H01L31/1864 , H01L29/1066
摘要： Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.
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公开(公告)号：US20210296258A1
公开(公告)日：2021-09-23
申请号：US17340425
申请日：2021-06-07
发明人： Wei-Yu Chien , Chien-Hsien Tseng , Dun-Nian Yaung , Nai-Wen Cheng , Pao-Tung Chen , Yi-Shin Chu , Yu-Yang Shen
IPC分类号： H01L23/552 , H01L23/538 , H01L29/06 , H01L21/768 , H01L21/762
摘要： Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components. Further, the shield structure substantially covers the second electronic component and/or would substantially cover the first electronic component if the semiconductor packaging device was flipped vertically.
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公开(公告)号：US10727164B2
公开(公告)日：2020-07-28
申请号：US16228585
申请日：2018-12-20
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Ching-Chun Wang , Kuan-Chieh Huang , Hsing-Chih Lin , Yi-Shin Chu
IPC分类号： H01L23/52 , H01L23/48 , H01L21/48 , H01L21/02 , H01L23/522 , H01L21/768
摘要： Present disclosure provides a semiconductor structure, including a semiconductor substrate having an active side, an interconnect layer in proximity to the active side of the semiconductor substrate, and a through substrate via extending from the semiconductor substrate to a first metal layer of the interconnect layer. The TSV being wider than the continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.
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