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1.发明申请METHODS, APPARATUS AND COMPUTER PROGRAM PRODUCTS FOR FABRICATING MASKS AND SEMICONDUCTOR DEVICES USING MODEL-BASED OPTICAL PROXIMITY EFFECT CORRECTION AND LITHOGRAPHY-FRIENDLY LAYOUT 有权使用基于模型的光学近似效应校正和平滑友好布局的方法，装置和计算机程序产品来制作掩模和半导体器件公开(公告)号：US20090087758A1
公开(公告)日：2009-04-02
申请号：US12238884
申请日：2008-09-26
申请人： Sung-soo Suh , Suk-joo Lee , Yong-hee Park , Mi-kyeong Lee
发明人： Sung-soo Suh , Suk-joo Lee , Yong-hee Park , Mi-kyeong Lee
CPC分类号： G03F1/36
摘要： Design rules for circuit patterns of a semiconductor device are identified, and schematic layouts of the circuit patterns are generated according to the design rules. Lithography friendly layout (LFL) circuit patterns are generated from the schematic layouts. Target layout circuit patterns are generated from the LFL circuit patterns. Optical proximity effect correction (OPC) is performed on the target layout circuit patterns to generate OPC circuit patterns. A mask is fabricated from the OPC circuit patterns, and may be used fabricate a semiconductor device.
摘要翻译： 识别半导体器件的电路图案的设计规则，根据设计规则生成电路图案的原理图布局。 从原理图布局生成光刻友好布局（LFL）电路图案。 目标布局电路图案是从LFL电路图形生成的。 对目标布局电路图案执行光学邻近效应校正（OPC）以产生OPC电路图案。 掩模由OPC电路图形制成，可用于制造半导体器件。
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2.发明授权Methods, apparatus and computer program products for fabricating masks and semiconductor devices using model-based optical proximity effect correction and lithography-friendly layout 有权使用基于模型的光学邻近效应校正和光刻友好布局制造掩模和半导体器件的方法，装置和计算机程序产品公开(公告)号：US08563197B2
公开(公告)日：2013-10-22
申请号：US12238884
申请日：2008-09-26
申请人： Sung-soo Suh , Suk-joo Lee , Yong-hee Park , Mi-kyeong Lee
发明人： Sung-soo Suh , Suk-joo Lee , Yong-hee Park , Mi-kyeong Lee
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Design rules for circuit patterns of a semiconductor device are identified, and schematic layouts of the circuit patterns are generated according to the design rules. Lithography friendly layout (LFL) circuit patterns are generated from the schematic layouts. Target layout circuit patterns are generated from the LFL circuit patterns. Optical proximity effect correction (OPC) is performed on the target layout circuit patterns to generate OPC circuit patterns. A mask is fabricated from the OPC circuit patterns, and may be used fabricate a semiconductor device.
摘要翻译： 识别半导体器件的电路图案的设计规则，根据设计规则生成电路图案的原理图布局。 从原理图布局生成光刻友好布局（LFL）电路图案。 目标布局电路图案是从LFL电路图形生成的。 对目标布局电路图案执行光学邻近效应校正（OPC）以产生OPC电路图案。 掩模由OPC电路图形制成，可用于制造半导体器件。
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公开(公告)号：US20160079354A1
公开(公告)日：2016-03-17
申请号：US14807912
申请日：2015-07-24
申请人： Yong-hee Park , Young-seok Song , Ji-soo Chang , Young-chul Hwang
发明人： Yong-hee Park , Young-seok Song , Ji-soo Chang , Young-chul Hwang
IPC分类号： H01L29/06 , H01L23/535 , H01L27/088
CPC分类号： H01L29/7856 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L27/0924 , H01L29/66545
摘要： An IC device includes a substrate including a device region having a fin-type active region and a deep trench region; a gate line that extends in a direction intersecting the fin-type active region; and an inter-device isolation layer that fills the deep trench region. The gate line includes a first gate portion that extends on the device region to cover the fin-type active region and has a flat upper surface at a first level and a second gate portion that extends on the deep trench region to cover the inter-device isolation layer while being integrally connected to the first gate portion and has an upper surface at a second level that is closer to the substrate than the first level.
摘要翻译： IC器件包括：衬底，其包括具有鳍型有源区和深沟槽区的器件区; 栅极线，其在与鳍式有源区域相交的方向上延伸; 以及填充深沟槽区域的器件间隔离层。 栅极线包括第一栅极部分，其在器件区域上延伸以覆盖鳍状有源区并且具有处于第一电平的平坦上表面和在深沟槽区域上延伸以覆盖器件间的第二栅极部分 隔离层，同时整体连接到第一栅极部分，并且具有比第一电平更靠近基板的第二电平的上表面。
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