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公开(公告)号：US11544543B2
公开(公告)日：2023-01-03
申请号：US16698984
申请日：2019-11-28
发明人： Zidong Du , Shengyuan Zhou , Shaoli Liu , Tianshi Chen
摘要： A computing device, comprising: a computing module, comprising one or more computing units; and a control module, comprising a computing control unit, and used for controlling shutdown of the computing unit of the computing module according to a determining condition. Also provided is a computing method. The computing device and method have the advantages of low power consumption and high flexibility, and can be combined with the upgrading mode of software, thereby further increasing the computing speed, reducing the computing amount, and reducing the computing power consumption of an accelerator.
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公开(公告)号：US11836497B2
公开(公告)日：2023-12-05
申请号：US16075836
申请日：2018-07-23
发明人： Bingrui Wang , Shengyuan Zhou , Yao Zhang
CPC分类号： G06F9/30181 , G06F9/3001 , G06F9/30007 , G06F9/30036 , G06F9/30145 , G06F17/16 , G06N3/063
摘要： There is provides an operation module, which includes a memory, a register unit, a dependency relationship processing unit, an operation unit, and a control unit. The memory is configured to store a vector, the register unit is configured to store an extension instruction, and the control unit is configured to acquire and parse the extension instruction, so as to obtain a first operation instruction and a second operation instruction. An execution sequence of the first operation instruction and the second operation instruction can be determined, and an input vector of the first operation instruction can be read from the memory. The operation unit is configured to convert an expression mode of the input data index of the first operation instruction and to screen data, and to execute the first and second operation instruction according to the execution sequence, so as to obtain an extension instruction.
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公开(公告)号：US11656910B2
公开(公告)日：2023-05-23
申请号：US16693999
申请日：2019-11-25
发明人： Tianshi Chen , Shengyuan Zhou , Shaoli Liu
CPC分类号： G06F9/505 , G06F9/4881 , G06F9/5066 , G06N3/02 , G06N3/04 , G06N3/08 , G06N5/01 , G06F2209/5017
摘要： The disclosure provides a task segmentation device and method, a task processing device and method, a multi-core processor. The task segmentation device includes a granularity task segmentation unit configured to segment a task by adopting at least one granularity to form subtasks, and a task segmentation granularity selection unit configured to select the granularity to be adopted.
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公开(公告)号：US11307866B2
公开(公告)日：2022-04-19
申请号：US16698998
申请日：2019-11-28
发明人： Shaoli Liu , Shengyuan Zhou , Zidong Du
IPC分类号： G06F9/302 , G06F17/16 , G06F9/38 , G06F9/30 , G06F3/01 , G06F9/48 , G06F9/50 , G06F9/54 , G06F11/07 , G06F11/10 , G06F11/30 , G06F12/0875 , G06K9/62 , G06N3/04 , G06N3/063 , G06V40/16 , G06F7/57 , G06F7/544 , G06F1/324
摘要： The disclosure provides a data processing device and method. The data processing device may include: a task configuration information storage unit and a task queue configuration unit. The task configuration information storage unit is configured to store configuration information of tasks. The task queue configuration unit is configured to configure a task queue according to the configuration information stored in the task configuration information storage unit. According to the disclosure, a task queue may be configured according to the configuration information.
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公开(公告)号：US20200097792A1
公开(公告)日：2020-03-26
申请号：US16697533
申请日：2019-11-27
发明人： Tianshi Chen , Shengyuan Zhou , Zidong Du , Qi Guo
摘要： The present disclosure relates to a processing device including a memory configured to store data to be computed; a computational circuit configured to compute the data to be computed, which includes performing acceleration computations on the data to be computed by using an adder circuit and a multiplier circuit; and a control circuit configured to control the memory and the computational circuit, which includes performing acceleration computations according to the data to be computed. The present disclosure may have high flexibility, good configurability, fast computational speed, low power consumption, and other features.
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公开(公告)号：US11727268B2
公开(公告)日：2023-08-15
申请号：US16698979
申请日：2019-11-28
发明人： Zai Wang , Shengyuan Zhou , Shuai Hu , Tianshi Chen
摘要： A computing device, comprising: a computing module, comprising one or more computing units; and a control module, comprising a computing control unit, and used for controlling shutdown of the computing unit of the computing module according to a determining condition. Also provided is a computing method. The computing device and method have the advantages of low power consumption and high flexibility, and can be combined with the upgrading mode of software, thereby further increasing the computing speed, reducing the computing amount, and reducing the computing power consumption of an accelerator.
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公开(公告)号：US11544542B2
公开(公告)日：2023-01-03
申请号：US16698976
申请日：2019-11-28
发明人： Zai Wang , Shengyuan Zhou , Zidong Du , Tianshi Chen
摘要： A computing device, comprising: a computing module, comprising one or more computing units; and a control module, comprising a computing control unit, and used for controlling shutdown of the computing unit of the computing module according to a determining condition. Also provided is a computing method. The computing device and method have the advantages of low power consumption and high flexibility, and can be combined with the upgrading mode of software, thereby further increasing the computing speed, reducing the computing amount, and reducing the computing power consumption of an accelerator.
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公开(公告)号：US20200097793A1
公开(公告)日：2020-03-26
申请号：US16697603
申请日：2019-11-27
发明人： Tianshi Chen , Shengyuan Zhou , Zidong Du , Qi Guo
摘要： The present disclosure relates to a fused vector multiplier for computing an inner product between vectors, where vectors to be computed are a multiplier number vector {right arrow over (A)}{AN . . . A2A1A0} and a multiplicand number {right arrow over (B)} {BN . . . B2B1B0}, {right arrow over (A)} and {right arrow over (B)} have the same dimension which is N+1. The multiplier includes: N+1 multiplication sub-units configured to perform multiplication on each dimension of a vector respectively, and take lower n bits of the multiplier number vector for multiplication each time, where the n bits are removed from the binary number of each dimension of the multiplier number vector after the n bits are taken, and n is larger than 1 and less than N+1; an adder tree configured to perform addition on results of N+1 multiplication sub-units obtained from a same operation each time; and a result register configured to hold a result of every addition performed by the adder tree and send the result to the adder tree for next computation.
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公开(公告)号：US11703939B2
公开(公告)日：2023-07-18
申请号：US16620540
申请日：2018-10-30
发明人： Tianshi Chen , Shuai Hu , Shengyuan Zhou , Xishan Zhang
CPC分类号： G06F3/01 , G06F40/30 , G06N3/06 , G06N20/00 , G06V40/20 , G10L15/22 , G10L15/26 , G10L2015/223
摘要： The present disclosure provides a signal processing device, including a signal collector, an instruction converter, and a processor. Examples of the present disclosure may achieve precise recognition of users' intentions and bring operational conveniences to users.
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公开(公告)号：US11531541B2
公开(公告)日：2022-12-20
申请号：US16697533
申请日：2019-11-27
发明人： Tianshi Chen , Shengyuan Zhou , Zidong Du , Qi Guo
摘要： The present disclosure relates to a processing device including a memory configured to store data to be computed; a computational circuit configured to compute the data to be computed, which includes performing acceleration computations on the data to be computed by using an adder circuit and a multiplier circuit; and a control circuit configured to control the memory and the computational circuit, which includes performing acceleration computations according to the data to be computed. The present disclosure may have high flexibility, good configurability, fast computational speed, low power consumption, and other features.
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