- 专利标题: PROCESSING APPARATUS AND PROCESSING METHOD
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申请号: US16697603申请日: 2019-11-27
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公开(公告)号: US20200097793A1公开(公告)日: 2020-03-26
- 发明人: Tianshi Chen , Shengyuan Zhou , Zidong Du , Qi Guo
- 申请人: Shanghai Cambricon Information Technology Co., Ltd.
- 优先权: CN201711468817.1 20170421
- 主分类号: G06N3/04
- IPC分类号: G06N3/04 ; G06N3/08
摘要:
The present disclosure relates to a fused vector multiplier for computing an inner product between vectors, where vectors to be computed are a multiplier number vector {right arrow over (A)}{AN . . . A2A1A0} and a multiplicand number {right arrow over (B)} {BN . . . B2B1B0}, {right arrow over (A)} and {right arrow over (B)} have the same dimension which is N+1. The multiplier includes: N+1 multiplication sub-units configured to perform multiplication on each dimension of a vector respectively, and take lower n bits of the multiplier number vector for multiplication each time, where the n bits are removed from the binary number of each dimension of the multiplier number vector after the n bits are taken, and n is larger than 1 and less than N+1; an adder tree configured to perform addition on results of N+1 multiplication sub-units obtained from a same operation each time; and a result register configured to hold a result of every addition performed by the adder tree and send the result to the adder tree for next computation.
公开/授权文献
- US11507350B2 Processing apparatus and processing method 公开/授权日:2022-11-22
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