公开(公告)号：US20060053244A1

公开(公告)日：2006-03-09

申请号：US10937752

申请日：2004-09-09

Applicant: Serge Fruhauf ,  Robert Leydier

Inventor： Serge Fruhauf ,  Robert Leydier

IPC: G06F13/20

CPC classification number: G06F13/4068

Abstract: A USB device, integrated circuit, smart card and method are disclosed. A USB transceiver is connected to a data interface and operable at a respective low speed and full speed configuration. A processor as a USB device controller is operatively connected to the low speed USB transceiver and full speed USB transceiver and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed operation is chosen.

Abstract translation: 公开了USB设备，集成电路，智能卡和方法。 USB收发器连接到数据接口并可在相应的低速和全速配置下操作。 作为USB设备控制器的处理器可操作地连接到低速USB收发器和全速USB收发器，并且可操作用于根据是否选择低速或高速操作来向USB主机发送不同的设备描述符以执行枚举。

公开(公告)号：US20080049606A1

公开(公告)日：2008-02-28

申请号：US11571466

申请日：2005-07-01

Applicant: Alain Rhelimi ,  Robert Leydier

Inventor： Alain Rhelimi ,  Robert Leydier

IPC: H04L5/14 ,  H03K7/08

CPC classification number: H04L5/14 ,  H04L5/1423 ,  H04L25/02 ,  H04L25/4902 ,  H04L25/4906

Abstract: A two-way communication device has a master transmitter (SysM1, TRM1, SysM2, TRM2) connected to at least one slave transmitter (SysS1, TRS1, SysS2, TRS2) by an active connection wire. The master transmitter and the slave transmitter have a common reference (GND). The master transmitter can transmit a master signal (S1) to the slave transmitter and the slave transmitter can transmit a slave signal (S2) to the master transmitter. The master signal (S1) is a digital modulation in voltage. The slave signal (S2) is a digital modulation in current.

Abstract translation: 双向通信装置具有通过有源连接线连接到至少一个从发送器（SysS 1，TRS 1，SysS 2，TRS 2）的主发送器（SysM 1，TRM 1，SysM 2，TRM 2）。 主发送器和从发送器具有公共参考（GND）。 主发送器可以将主信号（S1）发送到从发送器，从发送器可以将主信号（S 2）发送到主发送器。 主信号（S 1）是电压的数字调制。 从信号（S 2）是电流中的数字调制。

公开(公告)号：US06439464B1

公开(公告)日：2002-08-27

申请号：US09686925

申请日：2000-10-11

Applicant: Serge F. Fruhauf ,  Herve Goupil ,  Robert Leydier

Inventor： Serge F. Fruhauf ,  Herve Goupil ,  Robert Leydier

IPC: G06K1906

CPC classification number: G06K19/07733 ,  G06K19/07

Abstract: A dual-mode IC is provided for operating in first mode such as an ISO mode in accordance with International Standards Organization 7816 (ISO 7816) protocol, and a second, non-ISO mode, such as a USB mode in accordance with Universal Serial Bus (USB) protocol. The dual-mode IC is preferably in a smart card and includes a microprocessor, a switching block, and an external interface. The external interface includes a voltage supply pad, a reference voltage pad, a reset pad, a clock pad and an input/output pad in accordance with the ISO 7816 protocol, and a D-plus pad and D-minus pad in accordance with the USB protocol. The IC further includes a mode configuration circuit for detecting a USB mode condition on at least one of the D-plus and D-minus pads, and configuring the IC in the ISO mode or the USB mode depending on the result. Once the IC is configured in a particular mode, it will operate in only that mode until the next power-on reset sequence.

Abstract translation: 提供了一种双模式IC，用于按照国际标准组织7816（ISO 7816）协议的第一模式，例如ISO模式操作，以及第二，非ISO模式，例如根据通用串行总线的USB模式 （USB）协议。 双模IC优选地在智能卡中，并且包括微处理器，切换块和外部接口。 外部接口包括电压供应板，参考电压焊盘，复位焊盘，时钟焊盘和根据ISO 7816协议的输入/输出焊盘，以及根据ISO 7816协议的D-plus焊盘和D-minus焊盘 USB协议。 该IC还包括用于检测D-plus和D-minus焊盘中的至少一个的USB模式状态的模式配置电路，并且根据结果在ISO模式或USB模式下配置IC。 一旦将IC配置为特定模式，它将仅在该模式下运行，直到下一次上电复位序列。

公开(公告)号：US07656979B2

公开(公告)日：2010-02-02

申请号：US11325233

申请日：2006-01-04

Applicant: Robert Leydier ,  Alain Pomet

Inventor： Robert Leydier ,  Alain Pomet

IPC: H04L7/00

CPC classification number: H04L7/0337

Abstract: A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization value (SV) is representative of a number of cycles of the oscillator signal (OS) contained within a time interval for a unit of external data. The synchronization value (SV) is an initial value (IV) during an initial synchronization phase and a measured value (MV) during a measurement-based synchronization phase. A control circuit (IFC) carries out a calibration step in which the initial value (IV) is a preprogrammed reset value (RV) and in which the measured value (MV) is stored as a calibration value (CV). The control circuit (IFC) applies the calibration value (CV) as the initial value (IV) in subsequent initial synchronization phases.

Abstract translation: 数据通信装置包括：基于采样信号（SP）将外部数据（XDT）转换为内部数据（IDT）的输入电路（DRTC）。 同步电路（SYNC）基于振荡器信号（OS）和同步值（SV）提供采样信号（SP）。 同步值（SV）表示包含在外部数据单位的时间间隔内的振荡器信号（OS）的周期数。 同步值（SV）是在初始同步阶段期间的初始值（IV）和基于测量的同步阶段期间的测量值（MV）。 控制电路（IFC）执行校准步骤，其中初始值（IV）是预编程的复位值（RV），其中测量值（MV）被存储为校准值（CV）。 控制电路（IFC）将校准值（CV）作为初始值（IV）应用于后续的初始同步阶段。

公开(公告)号：US07282424B2

公开(公告)日：2007-10-16

申请号：US10494881

申请日：2002-11-06

Applicant: Béatrice Bonvalot ,  Sylvie Barbe ,  Laurent Le Moullec ,  Robert Leydier

Inventor： Béatrice Bonvalot ,  Sylvie Barbe ,  Laurent Le Moullec ,  Robert Leydier

IPC: H01L21/30

CPC classification number: H01L25/50 ,  H01L24/26 ,  H01L24/83 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/07802 ,  H01L2924/14

Abstract: A plurality of assemblies is manufactured. Each assembly comprises a sealing slice that is fixed to a base slice. The plurality of assemblies is manufactured in the following manner. In a preparation step, a stack is formed. The stack comprises a plurality of pre-assemblies. Each pre-assembly comprises a base slice, a sealing slice and a fixing layer provided between the base slice and the sealing slice. The stack further comprises at least one supple buffer layer. The supple buffer layer has a mechanical rigidity, which is substantially less than that of the base slices and that of the sealing slices. The supple buffer layer thus enables to compensate for variations in thickness of the base slices and of the sealing slices. In a fixing step, the stack is pressed which causes the sealing slice of each pre-assembly to be fixed to the base-slice of the pre-assembly.

Abstract translation: 制造多个组件。 每个组件包括固定到基片的密封片。 多个组件以如下方式制造。 在制备步骤中，形成堆叠。 堆叠包括多个预组件。 每个预组件包括基底切片，密封切片和设置在基底切片和密封切片之间的固定层。 堆叠还包括至少一个柔顺缓冲层。 柔软的缓冲层具有机械刚性，其基本上小于基底片和密封片的刚度。 柔性缓冲层因此能够补偿基底切片和密封切片的厚度变化。 在固定步骤中，按压堆叠，这使得每个预组件的密封片固定到预组件的基片上。

公开(公告)号：US06217685B1

公开(公告)日：2001-04-17

申请号：US09202269

申请日：1999-03-22

Applicant: Robert Leydier ,  Bertrand D'Arbonneau

Inventor： Robert Leydier ,  Bertrand D'Arbonneau

IPC: B32B3116

CPC classification number: G06K19/07745 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention concerns a method for inserting an electronic module (13) on a thermoplastic substrate (131) in a cavity (12) provided in a card with electronic memory in thermoplastic material. The invention is characterized in that it consists in the following steps: a) depositing in said cavity (12) an adhesive (14) for gluing the electronic module (13) thermoplastic substrate (131) on the card body (11) thermoplastic material; b) arranging the electronic module (13) in the cavity (12); c) simultaneously applying a pressing force (F) on the electronic module (13) and ultrasonic energy (US) on the cavity (12) thermoplastic material, in contact with the electronic module (13) thermoplastic substrate (131). The invention is useful for making cards with electronic memory.

Abstract translation: 本发明涉及一种用于将电子模块（13）插入设置在具有热塑性材料的电子存储器的卡中的空腔（12）中的热塑性基材（131）上的方法。 本发明的特征在于其包括以下步骤：a）在所述空腔（12）中沉积粘合剂（14），用于将电子模块（13）热塑性基材（131）胶合在卡体（11）热塑性材料上; b）将电子模块（13）布置在空腔（12）中; c）在所述电子模块（13）上同时施加压力（F）和所述空腔（12）热塑性材料上与所述电子模块（13）热塑性基底（131）接触的超声波能量（US）。 本发明对于具有电子存储器的卡是有用的。

公开(公告)号：US5223444A

公开(公告)日：1993-06-29

申请号：US761119

申请日：1991-09-17

Applicant: Vincent Mosser ,  Ian Suski ,  Joseph Goss ,  Robert Leydier

Inventor： Vincent Mosser ,  Ian Suski ,  Joseph Goss ,  Robert Leydier

IPC: G01L1/22 ,  G01L9/00

CPC classification number: G01L1/2293 ,  G01L9/0042 ,  G01L9/0055 ,  Y10T29/42 ,  Y10T29/49103

Abstract: The method of making a pressure sensor formed of semiconductor material on an insulating support, i.e., as a semiconductor-on-silicon, is described. The sensor is comprised of four piezoresistive gauges formed in the semiconductor material. Two of the gauges, each have a pair of limbs joined by a base, such that they are U-shaped, and two others are I-shaped. Each of the four gauges comprise two half-gauges, and each half-gauge comprises an elongated sensing zone in semiconductor material and having a reduced width in the plane of the insulating support. Two ohmic contact zones are disposed at the ends of each of the half-gauges, and two connection zones in semiconductor material and of greater width are disposed between the sensing zones and the ohmic contact zones, the form of the two connection zones are the same for each of the eight half-gauges.

Abstract translation: 描述了在半导体材料上形成的绝缘支撑体（即，作为硅上半导体）形成压力传感器的方法。 传感器由形成在半导体材料中的四个压阻计组成。 两个量规，每个都有一对四肢，由一个基座连接，使得它们是U形的，另外两个是I形的。 四个量规中的每一个包括两个半计，每个半计包括半导体材料中的细长感测区域，并且在绝缘支撑件的平面中具有减小的宽度。 两个欧姆接触区域设置在每个半计的端部，并且半导体材料中的两个连接区域和较大宽度设置在感测区域和欧姆接触区域之间，两个连接区域的形式相同 对于八个半计的每一个。

公开(公告)号：US20100281197A1

公开(公告)日：2010-11-04

申请号：US12809898

申请日：2007-12-21

Applicant: Robert Leydier ,  Alain Pomet ,  Benjamin Duval

Inventor： Robert Leydier ,  Alain Pomet ,  Benjamin Duval

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4027

Abstract: A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state output buffer 12, 13 linked to the first data port, a second transceiver stage 50 comprising at least one input buffer 21, 24 and at least one tri-state output buffer 12, 13 linked to the second data port, a first detection circuit 31 for detecting the arrival of a packet by the first data port, a second detection circuit 37 for detecting the arrival of a packet by the second data port. A selection circuitry 34, 35 enables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.

Abstract translation: 桥电路10设置在第一数据端口A1，A2和第二数据端口B1，B2之间。 桥接电路包括第一收发器级40，其包括至少一个输入缓冲器11,14和与第一数据端口链接的至少一个三态输出缓冲器12,13;第二收发器级50，包括至少一个输入缓冲器21， 24和连接到第二数据端口的至少一个三态输出缓冲器12,13，用于检测第一数据端口到达分组的第一检测电路31，用于检测分组到达的第二检测电路37 由第二个数据端口。 选择电路34,35可以根据由第一和第二检测电路进行的检测来输出第一或第二收发器级的三态输出缓冲器。

公开(公告)号：US20080231328A1

公开(公告)日：2008-09-25

申请号：US12089897

申请日：2006-06-10

Applicant: Robert Leydier ,  Alain Pomet ,  Benjamin Duval

Inventor： Robert Leydier ,  Alain Pomet ,  Benjamin Duval

IPC: H03B21/00 ,  G06F1/04 ,  G06K19/067

CPC classification number: G06F1/04 ,  H03K5/133 ,  H03K5/135 ,  H03K5/156 ,  H03K2005/00058 ,  H04L7/0338

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal φ(0) to φ(2i-1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal φ(0) to j(2i-1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal φ(0) to φ(2i-1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

Abstract translation: 一个延迟电路插入时钟恢复电路内的开环，以提高时钟恢复的精度。 一个振荡器信号phi（0）到phi（2I i-1）被提供有基本的时间步骤。 在接收的比特流中测量对应于比特持续时间的时间步长的合理数量。 振荡器信号phi（0）至j（2-i-1）被转换成具有与所述时钟信号的有效边沿同时具有至少一个振荡器信号phi（0）至phi （2 1>），两个连续的有效边沿被分开与时间步长数的整数部分成比例的时间长度。 计算时间延迟与时间步长数的小数部分成比例。 时钟信号CK的下一个有效沿延迟所述计算的延迟。