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1.发明授权Method and circuit for local clock generation and smartcard including it thereon 有权用于本地时钟产生的方法和电路以及包括其上的智能卡公开(公告)号：US07881894B2
公开(公告)日：2011-02-01
申请号：US12089897
申请日：2006-06-10
Applicant: Robert Leydier , Alain Pomet , Benjamin Duval
Inventor： Robert Leydier , Alain Pomet , Benjamin Duval
IPC: G06F1/04
CPC classification number: G06F1/04 , H03K5/133 , H03K5/135 , H03K5/156 , H03K2005/00058 , H04L7/0338
Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal φ(0) to φ(2i−1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal φ(0) to j(2i−1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal φ(0) to φ(2i−1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.
Abstract translation: 一个延迟电路插入时钟恢复电路内的开环，以提高时钟恢复的精度。 一个振荡器信号（0）到＆phgr;（2i-1）被提供有基本的时间步。 在接收的比特流中测量对应于比特持续时间的时间步长的合理数量。 将振荡器信号＆phgr（0）〜j（2i-1）变换成具有与所述时钟信号的有效边沿同步的时钟信号CK与至少一个振荡器信号（0）到（2i-1） 两个连续的有效边沿被分离成与时间步长数的整数部分成比例的时间长度。 计算时间延迟与时间步长数的小数部分成比例。 时钟信号CK的下一个有效沿延迟所述计算的延迟。
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公开(公告)号：US20100281197A1
公开(公告)日：2010-11-04
申请号：US12809898
申请日：2007-12-21
Applicant: Robert Leydier , Alain Pomet , Benjamin Duval
Inventor： Robert Leydier , Alain Pomet , Benjamin Duval
CPC classification number: G06F13/4027
Abstract: A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state output buffer 12, 13 linked to the first data port, a second transceiver stage 50 comprising at least one input buffer 21, 24 and at least one tri-state output buffer 12, 13 linked to the second data port, a first detection circuit 31 for detecting the arrival of a packet by the first data port, a second detection circuit 37 for detecting the arrival of a packet by the second data port. A selection circuitry 34, 35 enables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.
Abstract translation: 桥电路10设置在第一数据端口A1，A2和第二数据端口B1，B2之间。 桥接电路包括第一收发器级40，其包括至少一个输入缓冲器11,14和与第一数据端口链接的至少一个三态输出缓冲器12,13;第二收发器级50，包括至少一个输入缓冲器21， 24和连接到第二数据端口的至少一个三态输出缓冲器12,13，用于检测第一数据端口到达分组的第一检测电路31，用于检测分组到达的第二检测电路37 由第二个数据端口。 选择电路34,35可以根据由第一和第二检测电路进行的检测来输出第一或第二收发器级的三态输出缓冲器。
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3.发明申请Method and Circuit for Local Clock Generation and Smartcard Including it Thereon 有权本地时钟产生方法和电路及其中包含的智能卡公开(公告)号：US20080231328A1
公开(公告)日：2008-09-25
申请号：US12089897
申请日：2006-06-10
Applicant: Robert Leydier , Alain Pomet , Benjamin Duval
Inventor： Robert Leydier , Alain Pomet , Benjamin Duval
IPC: H03B21/00 , G06F1/04 , G06K19/067
CPC classification number: G06F1/04 , H03K5/133 , H03K5/135 , H03K5/156 , H03K2005/00058 , H04L7/0338
Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal φ(0) to φ(2i-1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal φ(0) to j(2i-1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal φ(0) to φ(2i-1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.
Abstract translation: 一个延迟电路插入时钟恢复电路内的开环，以提高时钟恢复的精度。 一个振荡器信号phi（0）到phi（2I i-1）被提供有基本的时间步骤。 在接收的比特流中测量对应于比特持续时间的时间步长的合理数量。 振荡器信号phi（0）至j（2-i-1）被转换成具有与所述时钟信号的有效边沿同时具有至少一个振荡器信号phi（0）至phi （2 1>），两个连续的有效边沿被分开与时间步长数的整数部分成比例的时间长度。 计算时间延迟与时间步长数的小数部分成比例。 时钟信号CK的下一个有效沿延迟所述计算的延迟。
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公开(公告)号：US07656979B2
公开(公告)日：2010-02-02
申请号：US11325233
申请日：2006-01-04
Applicant: Robert Leydier , Alain Pomet
Inventor： Robert Leydier , Alain Pomet
IPC: H04L7/00
CPC classification number: H04L7/0337
Abstract: A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization value (SV) is representative of a number of cycles of the oscillator signal (OS) contained within a time interval for a unit of external data. The synchronization value (SV) is an initial value (IV) during an initial synchronization phase and a measured value (MV) during a measurement-based synchronization phase. A control circuit (IFC) carries out a calibration step in which the initial value (IV) is a preprogrammed reset value (RV) and in which the measured value (MV) is stored as a calibration value (CV). The control circuit (IFC) applies the calibration value (CV) as the initial value (IV) in subsequent initial synchronization phases.
Abstract translation: 数据通信装置包括：基于采样信号（SP）将外部数据（XDT）转换为内部数据（IDT）的输入电路（DRTC）。 同步电路（SYNC）基于振荡器信号（OS）和同步值（SV）提供采样信号（SP）。 同步值（SV）表示包含在外部数据单位的时间间隔内的振荡器信号（OS）的周期数。 同步值（SV）是在初始同步阶段期间的初始值（IV）和基于测量的同步阶段期间的测量值（MV）。 控制电路（IFC）执行校准步骤，其中初始值（IV）是预编程的复位值（RV），其中测量值（MV）被存储为校准值（CV）。 控制电路（IFC）将校准值（CV）作为初始值（IV）应用于后续的初始同步阶段。
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公开(公告)号：US08412873B2
公开(公告)日：2013-04-02
申请号：US12809898
申请日：2007-12-21
Applicant: Robert Leydier , Alain Pomet , Benjamin Duval
Inventor： Robert Leydier , Alain Pomet , Benjamin Duval
CPC classification number: G06F13/4027
Abstract: A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state output buffer 12, 13 linked to the first data port, a second transceiver stage 50 comprising at least one input buffer 21, 24 and at least one tri-state output buffer 12, 13 linked to the second data port, a first detection circuit 31 for detecting the arrival of a packet by the first data port, a second detection circuit 37 for detecting the arrival of a packet by the second data port. A selection circuitry 34, 35 enables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.
Abstract translation: 桥电路10设置在第一数据端口A1，A2和第二数据端口B1，B2之间。 桥接电路包括第一收发器级40，其包括至少一个输入缓冲器11,14和与第一数据端口链接的至少一个三态输出缓冲器12,13;第二收发器级50，包括至少一个输入缓冲器21， 24和连接到第二数据端口的至少一个三态输出缓冲器12,13，用于检测第一数据端口到达分组的第一检测电路31，用于检测分组到达的第二检测电路37 由第二个数据端口。 选择电路34,35可以根据由第一和第二检测电路进行的检测来输出第一或第二收发器级的三态输出缓冲器。
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Patent Agency Ranking
6.发明授权Method and device for generating a random number in a USB (universal serial bus) peripheral 有权用于在USB（通用串行总线）外设中产生随机数的方法和装置公开(公告)号：US07958175B2
公开(公告)日：2011-06-07
申请号：US11653185
申请日：2007-01-12
Applicant: Alain Pomet , Benjamin Duval , Robert Leydier
Inventor： Alain Pomet , Benjamin Duval , Robert Leydier
IPC: G06F1/02
CPC classification number: G06F7/588
Abstract: A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.
Abstract translation: 一种用于产生随机数的方法，包括以下步骤：接收经历相位抖动的数据传输二进制信号，产生基本上具有相同平均频率的几个振荡器信号，并具有不同的相位，在出现时对每个振荡器信号的状态进行采样 的二进制信号的边沿，并且使用每个振荡器信号的状态来产生随机数。 该方法可以应用于可用于智能卡的集成电路。
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7.发明申请Method and device for generating a random number in a USB (Universal Serial Bus) peripheral 有权用于在USB（通用串行总线）外设中产生随机数的方法和装置公开(公告)号：US20090089347A1
公开(公告)日：2009-04-02
申请号：US11653185
申请日：2007-01-12
Applicant: Alain Pomet , Benjamin Duval , Robert Leydier
Inventor： Alain Pomet , Benjamin Duval , Robert Leydier
IPC: G06F7/58
CPC classification number: G06F7/588
Abstract: A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.
Abstract translation: 一种用于产生随机数的方法，包括以下步骤：接收经历相位抖动的数据传输二进制信号，产生基本上具有相同平均频率的几个振荡器信号，并具有不同的相位，在出现时对每个振荡器信号的状态进行采样 的二进制信号的边沿，并且使用每个振荡器信号的状态来产生随机数。 该方法可以应用于可用于智能卡的集成电路。
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公开(公告)号：US20060146968A1
公开(公告)日：2006-07-06
申请号：US11325233
申请日：2006-01-04
Applicant: Robert Leydier , Alain Pomet
Inventor： Robert Leydier , Alain Pomet
IPC: H04L7/00
CPC classification number: H04L7/0337
Abstract: A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization value (SV) is representative of a number of cycles of the oscillator signal (OS) contained within a time interval for a unit of external data. The synchronization value (SV) is an initial value (IV) during an initial synchronization phase and a measured value (MV) during a measurement-based synchronization phase. A control circuit (IFC) carries out a calibration step in which the initial value (IV) is a preprogrammed reset value (RV) and in which the measured value (MV) is stored as a calibration value (CV). The control circuit (IFC) applies the calibration value (CV) as the initial value (IV) in subsequent initial synchronization phases.
Abstract translation: 数据通信装置包括：基于采样信号（SP）将外部数据（XDT）转换为内部数据（IDT）的输入电路（DRTC）。 同步电路（SYNC）基于振荡器信号（OS）和同步值（SV）提供采样信号（SP）。 同步值（SV）表示包含在外部数据单位的时间间隔内的振荡器信号（OS）的周期数。 同步值（SV）是在初始同步阶段期间的初始值（IV）和基于测量的同步阶段期间的测量值（MV）。 控制电路（IFC）执行校准步骤，其中初始值（IV）是预编程的复位值（RV），其中测量值（MV）被存储为校准值（CV）。 控制电路（IFC）将校准值（CV）作为初始值（IV）应用于后续的初始同步阶段。
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公开(公告)号：US07941639B2
公开(公告)日：2011-05-10
申请号：US11481432
申请日：2006-07-05
Applicant: Yannick Teglia , Pierre-Yvan Liardet , Alain Pomet
Inventor： Yannick Teglia , Pierre-Yvan Liardet , Alain Pomet
IPC: G06F9/30
CPC classification number: G06F21/77 , G06F11/0757 , G06F21/75 , G06Q20/341 , G07F7/082 , G07F7/084 , G07F7/1008
Abstract: A method for protecting the execution of a main program against possible traps, including, on occurrence of an instruction from the main program, starting a time counter of a given count according to next instructions of the main program, and executing, once the counter has reached its count, at least one instruction of a secondary program from which the result of the main program depends.
Abstract translation: 一种用于保护主程序的执行免受可能的陷阱的方法，包括在发生来自主程序的指令时，根据主程序的下一个指令启动给定计数的时间计数器，一旦计数器具有 达到其计数，至少一个辅助程序的指令，主程序的结果从该程序所依赖。
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公开(公告)号：US06362671B1
公开(公告)日：2002-03-26
申请号：US09771364
申请日：2001-01-26
Applicant: Alexandre Malherbe , Fabrice Marinet , Alain Pomet
Inventor： Alexandre Malherbe , Fabrice Marinet , Alain Pomet
IPC: H03K501
Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.
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