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    BACKGROUND READS TO CONDITION PROGRAMMED SEMICONDUCTOR MEMORY CELLS
    2.
    发明申请
    BACKGROUND READS TO CONDITION PROGRAMMED SEMICONDUCTOR MEMORY CELLS 审中-公开

    公开(公告)号：US20180225164A1

    公开(公告)日：2018-08-09

    申请号：US15498595

    申请日：2017-04-27

    Applicant: Seagate Technology, LLC

    Inventor： Antoine Khoueir ,  Stacey Secatch ,  Kevin Gomez ,  Ryan Goss

    IPC: G06F11/07 ,  G11C16/16 ,  G11C16/34 ,  G11C16/26

    CPC classification number: G06F11/076 ,  G06F11/073 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459

    Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.

    Cross-point resistive-based memory architecture
    3.
    发明授权
    Cross-point resistive-based memory architecture 有权
    交叉点电阻式存储架构

    公开(公告)号：US08949567B2

    公开(公告)日：2015-02-03

    申请号：US13777137

    申请日：2013-02-26

    Applicant: Seagate Technology LLC

    Inventor： Antoine Khoueir ,  Jon D. Trantham ,  Kevin Gomez ,  Ara Patapoutian

    IPC: G06F13/00 ,  G06F12/00

    CPC classification number: G06F12/00 ,  G06F12/0238

    Abstract: A plurality of addressable memory tiles each comprise one or more cross-point arrays. Each array comprises a plurality of non-volatile resistance-change memory cells. A controller is configured to couple to the array and to a host system. The controller is configured to perform receiving, from the host system, one or more data objects each having a size equal to a predetermined logical block size, and storing the one or more data objects in a corresponding integer number of one or more of the memory tiles.

    Abstract translation: 多个可寻址存储器块各自包括一个或多个交叉点阵列。 每个阵列包括多个非易失性电阻变化存储单元。 控制器被配置为耦合到阵列和主机系统。 控制器被配置为执行从主机系统接收每个具有等于预定逻辑块大小的大小的一个或多个数据对象，并且将一个或多个数据对象存储在相应整数个存储器中的一个或多个存储器中 瓷砖。

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