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公开(公告)号:US11295202B2
公开(公告)日:2022-04-05
申请号:US14626172
申请日:2015-02-19
摘要: An apparatus comprises a mass storage unit and a plurality of circuit modules including a machine learning module, a programmable state machine module, and input/output interfaces. Switching circuitry is configured to selectively couple the circuit modules. Configuration circuitry is configured to access configuration data from the mass storage unit and to operate the switching circuitry to connect the circuit modules according to the configuration data.
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公开(公告)号:US20160098646A1
公开(公告)日:2016-04-07
申请号:US14506972
申请日:2014-10-06
CPC分类号: G06N20/00 , G06N3/0454 , G06N7/005 , H04L67/10 , H04L67/141
摘要: A connection between a user device and a network server is established. Via the connection, a deep learning network is formed for a processing task. A first portion of the deep learning network operates on the user device and a second portion of the deep learning network operates on the network server. Based on cooperation between the user device and the network server, a boundary between the first portion and the second portion of the deep learning network is dynamically modified based on a change in a performance indicator that could affect the processing task
摘要翻译: 建立用户设备与网络服务器之间的连接。 通过连接,形成了用于处理任务的深度学习网络。 深度学习网络的第一部分在用户设备上操作,并且深度学习网络的第二部分在网络服务器上操作。 基于用户设备和网络服务器之间的协作,基于可能影响处理任务的性能指标的变化来动态地修改深度学习网络的第一部分和第二部分之间的边界
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公开(公告)号:US09727459B2
公开(公告)日:2017-08-08
申请号:US14466143
申请日:2014-08-22
发明人: Antoine Khoueir , Ryan James Goss , Jon Trantham , Kevin Gomez , Frank Dropps
CPC分类号: G06F12/06 , G06F3/0619 , G06F3/064 , G06F3/0655 , G06F3/0679 , G06F12/00 , G06F12/0638 , G06F2206/1014 , G11C7/00 , G11C7/1006 , G11C15/046 , G11C16/0483 , G11C16/26 , G11C2211/5641
摘要: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.
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公开(公告)号:US20160020192A1
公开(公告)日:2016-01-21
申请号:US14334390
申请日:2014-07-17
发明人: Frank Dropps
IPC分类号: H01L25/065 , H01L21/768 , H01L23/532 , H01L25/00 , H01L23/538
CPC分类号: H01L25/0657 , H01L23/5328 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/50 , H01L2224/24145 , H01L2224/24226 , H01L2224/245 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49174 , H01L2224/73265 , H01L2224/73267 , H01L2224/83191 , H01L2224/92244 , H01L2225/06524 , H01L2225/06551 , H01L2924/00014 , H01L2924/1433 , H01L2924/1434 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要: A computing component may consist of a die package that has at least a board, first computing layer, and second computing layer. Dielectric layers can separate each of the board, first computing layer, and second computing layer. The first computing layer may be disposed between the board and second computing layer. One or more interconnects can continuously extend from the second computing layer to the board with a non-circular cross-section shape.
摘要翻译: 计算部件可以由至少具有板,第一计算层和第二计算层的管芯封装构成。 电介质层可分离板,第一计算层和第二计算层中的每一个。 第一计算层可以设置在板和第二计算层之间。 一个或多个互连件可以从第二计算层连续地延伸到具有非圆形横截面形状的板。
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公开(公告)号:US20150324691A1
公开(公告)日:2015-11-12
申请号:US14704124
申请日:2015-05-05
摘要: A system includes a plurality of nonvolatile memory cells and a map that assigns connections between nodes of a neural network to the memory cells. Memory devices containing nonvolatile memory cells and applicable circuitry for reading and writing may operate with the map. Information stored in the memory cells can represent weights of the connections. One or more neural processors can be present and configured to implement the neural network.
摘要翻译: 系统包括多个非易失性存储器单元和将神经网络的节点之间的连接分配给存储器单元的映射。 包含非易失性存储单元的存储器件和用于读取和写入的适用电路可以与地图一起操作。 存储在存储单元中的信息可以表示连接的权重。 可以存在并配置一个或多个神经处理器来实现神经网络。
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公开(公告)号:US10679140B2
公开(公告)日:2020-06-09
申请号:US14506972
申请日:2014-10-06
摘要: A connection between a user device and a network server is established. Via the connection, a deep learning network is formed for a processing task. A first portion of the deep learning network operates on the user device and a second portion of the deep learning network operates on the network server. Based on cooperation between the user device and the network server, a boundary between the first portion and the second portion of the deep learning network is dynamically modified based on a change in a performance indicator that could affect the processing task.
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公开(公告)号:US20160247080A1
公开(公告)日:2016-08-25
申请号:US14626172
申请日:2015-02-19
CPC分类号: G06N3/0472 , G06N3/063
摘要: An apparatus comprises a mass storage unit and a plurality of circuit modules including a machine learning module, a programmable state machine module, and input/output interfaces. Switching circuitry is configured to selectively couple the circuit modules. Configuration circuitry is configured to access configuration data from the mass storage unit and to operate the switching circuitry to connect the circuit modules according to the configuration data.
摘要翻译: 一种装置包括大容量存储单元和包括机器学习模块,可编程状态机模块和输入/输出接口的多个电路模块。 开关电路被配置为选择性地耦合电路模块。 配置电路被配置为从大容量存储单元访问配置数据并且操作开关电路以根据配置数据连接电路模块。
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公开(公告)号:US09305901B2
公开(公告)日:2016-04-05
申请号:US14334390
申请日:2014-07-17
发明人: Frank Dropps
IPC分类号: H01L23/50 , H01L25/00 , H01L25/065 , H01L23/538 , H01L23/532 , H01L21/768
CPC分类号: H01L25/0657 , H01L23/5328 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/50 , H01L2224/24145 , H01L2224/24226 , H01L2224/245 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49174 , H01L2224/73265 , H01L2224/73267 , H01L2224/83191 , H01L2224/92244 , H01L2225/06524 , H01L2225/06551 , H01L2924/00014 , H01L2924/1433 , H01L2924/1434 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要: A computing component may consist of a die package that has at least a board, first computing layer, and second computing layer. Dielectric layers can separate each of the board, first computing layer, and second computing layer. The first computing layer may be disposed between the board and second computing layer. One or more interconnects can continuously extend from the second computing layer to the board with a non-circular cross-section shape.
摘要翻译: 计算部件可以由至少具有板,第一计算层和第二计算层的管芯封装构成。 电介质层可分离板,第一计算层和第二计算层中的每一个。 第一计算层可以设置在板和第二计算层之间。 一个或多个互连件可以从第二计算层连续地延伸到具有非圆形横截面形状的板。
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公开(公告)号:US20160054940A1
公开(公告)日:2016-02-25
申请号:US14466143
申请日:2014-08-22
发明人: Antoine Khoueir , Ryan James Goss , Jon Trantham , Kevin Gomez , Frank Dropps
CPC分类号: G06F12/06 , G06F3/0619 , G06F3/064 , G06F3/0655 , G06F3/0679 , G06F12/00 , G06F12/0638 , G06F2206/1014 , G11C7/00 , G11C7/1006 , G11C15/046 , G11C16/0483 , G11C16/26 , G11C2211/5641
摘要: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.
摘要翻译: 第一和第二数据表示存储在非易失性固态存储器的第一和第二块中。 第一和第二块共享串联连接的位线。 选择第一和第二块,取消选择共享位线的非易失性固态存储器的其他块。 读取位线以确定第一和第二数据表示的组合。 组合可以包括联合或交集。
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