公开(公告)号：US20100020601A1

公开(公告)日：2010-01-28

申请号：US12471729

申请日：2009-05-26

申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C2211/5641

摘要： A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

摘要翻译： 非易失性存储器件包括被配置为支持单位和多位编程状态的非易失性存储器单元的阵列。 提供了一种控制电路，其被配置为在第一编程操作期间将阵列中的第一页非易失性存储单元编程为M位单元，并且还被配置为将第一页非易失性存储单元编程为N- 在第二次编程操作期间。 第一和第二编程操作通过至少一个擦除非易失性存储器单元的第一页的操作在时间上被分离。 M和N是不等于零的整数。

公开(公告)号：US08315102B2

公开(公告)日：2012-11-20

申请号：US13289689

申请日：2011-11-04

申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C2211/5641

摘要： A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

摘要翻译： 非易失性存储器件包括被配置为支持单位和多位编程状态的非易失性存储器单元的阵列。 提供了一种控制电路，其被配置为在第一编程操作期间将阵列中的第一页非易失性存储单元编程为M位单元，并且还被配置为将第一页非易失性存储单元编程为N- 在第二次编程操作期间。 第一和第二编程操作通过至少一个擦除非易失性存储器单元的第一页的操作在时间上被分离。 M和N是不等于零的整数。

公开(公告)号：US08072804B2

公开(公告)日：2011-12-06

申请号：US12471729

申请日：2009-05-26

申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C2211/5641

摘要： A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

摘要翻译： 非易失性存储器件包括被配置为支持单位和多位编程状态的非易失性存储器单元的阵列。 提供了一种控制电路，其被配置为在第一编程操作期间将阵列中的第一页非易失性存储单元编程为M位单元，并且还被配置为将第一页非易失性存储单元编程为N- 在第二次编程操作期间。 第一和第二编程操作通过至少一个擦除非易失性存储器单元的第一页的操作在时间上被分离。 M和N是不等于零的整数。

公开(公告)号：US20080237685A1

公开(公告)日：2008-10-02

申请号：US11822548

申请日：2007-07-06

申请人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

发明人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.

摘要翻译： 在一个实施例中，半导体存储器件包括具有突出部分的半导体衬底，在至少一个突出半导体衬底部分上形成的隧道绝缘层，以及设置在隧道绝缘层上的浮动栅极结构。 浮动栅极结构的上部比浮动栅极结构的下部宽，并且浮动栅极结构的下部具有小于隧道绝缘层的宽度的宽度。 第一绝缘层部分形成在半导体衬底中并从半导体衬底突出，使得浮栅结构设置在突出的第一绝缘层部分之间。 在第一绝缘层部分和浮动栅极结构之上形成电介质层，并且在电介质层上形成控制栅极。

公开(公告)号：US08809932B2

公开(公告)日：2014-08-19

申请号：US11822548

申请日：2007-07-06

申请人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

发明人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.

摘要翻译： 在一个实施例中，半导体存储器件包括具有突出部分的半导体衬底，在至少一个突出半导体衬底部分上形成的隧道绝缘层，以及设置在隧道绝缘层上的浮动栅极结构。 浮动栅极结构的上部比浮动栅极结构的下部宽，并且浮动栅极结构的下部具有小于隧道绝缘层的宽度的宽度。 第一绝缘层部分形成在半导体衬底中并从半导体衬底突出，使得浮栅结构设置在突出的第一绝缘层部分之间。 在第一绝缘层部分和浮动栅极结构之上形成电介质层，并且在电介质层上形成控制栅极。

公开(公告)号：US08059469B2

公开(公告)日：2011-11-15

申请号：US12481916

申请日：2009-06-10

申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jeong-Dong Choe ,  Tae-Yong Kim ,  Woo-Jung Kim ,  Dong-Hoon Jang ,  Young-Bae Yoon ,  Ki-Hyun Kim ,  Min-Tai Yu

发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jeong-Dong Choe ,  Tae-Yong Kim ,  Woo-Jung Kim ,  Dong-Hoon Jang ,  Young-Bae Yoon ,  Ki-Hyun Kim ,  Min-Tai Yu

IPC分类号： G11C11/34

CPC分类号： H01L27/11573 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L29/78

摘要： A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.

摘要翻译： 半导体器件包括限定在衬底中的驱动有源区和设置在驱动有源区的至少三个驱动晶体管。 驱动晶体管共享一个共同的源极/漏极，并且每个驱动晶体管包括彼此独立的各个源极/漏极。 公共源极/漏极和各个源极/漏极设置在驱动有源区域中。

公开(公告)号：US20100008152A1

公开(公告)日：2010-01-14

申请号：US12481916

申请日：2009-06-10

申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jeong-Dong Choe ,  Tae-Yong Kim ,  Woo-Jung Kim ,  Dong-Hoon Jang ,  Young-Bae Yoon ,  Ki-Hyun Kim ,  Min-Tai Yu

发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jeong-Dong Choe ,  Tae-Yong Kim ,  Woo-Jung Kim ,  Dong-Hoon Jang ,  Young-Bae Yoon ,  Ki-Hyun Kim ,  Min-Tai Yu

IPC分类号： G11C11/4096 ,  G11C5/06

CPC分类号： H01L27/11573 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L29/78

摘要： A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.

摘要翻译： 半导体器件包括限定在衬底中的驱动有源区和设置在驱动有源区的至少三个驱动晶体管。 驱动晶体管共享一个共同的源极/漏极，并且每个驱动晶体管包括彼此独立的各个源极/漏极。 公共源极/漏极和各个源极/漏极设置在驱动有源区域中。

公开(公告)号：US08044908B2

公开(公告)日：2011-10-25

申请号：US12013151

申请日：2008-01-11

申请人： Se-Hoon Lee

发明人： Se-Hoon Lee

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/2092 ,  G09G2300/0417 ,  G09G2310/0289 ,  G09G2310/06 ,  G09G2320/0233 ,  G09G2330/02

摘要： A liquid crystal display device includes a timing controller generating a voltage compensation control pulse and a gate control signal, a voltage compensation signal generator generating a voltage compensation signal, the voltage level of which is gradually reduced during one frame period, in response to the voltage compensation control pulse, a power unit outputting a gate-on voltage to a plurality of gate lines by gradually increasing the level of the gate-on voltage in response to the voltage compensation signal, and a gate driver sequentially supplying the gate-on voltage to the plurality of gate lines in response to the gate control signal.

摘要翻译： 液晶显示装置包括产生电压补偿控制脉冲和栅极控制信号的定时控制器，产生电压补偿信号的电压补偿信号发生器，其电压电平在一个帧周期期间响应电压逐渐减小 补偿控制脉冲，功率单元，通过响应于电压补偿信号逐渐增加栅极导通电压的电平，向多条栅极线输出栅极导通电压，以及栅极驱动器，顺序地将栅极导通电压提供给 多个栅极线响应于栅极控制信号。

公开(公告)号：US07902024B2

公开(公告)日：2011-03-08

申请号：US11896982

申请日：2007-09-07

申请人： Se-Hoon Lee ,  Donghoon Jang ,  Jong Jin Lee ,  Jeong-Dong Choe

发明人： Se-Hoon Lee ,  Donghoon Jang ,  Jong Jin Lee ,  Jeong-Dong Choe

IPC分类号： H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

摘要： A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.

摘要翻译： 存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅 浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。

公开(公告)号：US08330205B2

公开(公告)日：2012-12-11

申请号：US13040380

申请日：2011-03-04

申请人： Se-Hoon Lee ,  Donghoon Jang ,  Jong Jin Lee ,  Jeong-Dong Choe

发明人： Se-Hoon Lee ,  Donghoon Jang ,  Jong Jin Lee ,  Jeong-Dong Choe

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

摘要： A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.

摘要翻译： 存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅 浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。