公开(公告)号：US20080237685A1

公开(公告)日：2008-10-02

申请号：US11822548

申请日：2007-07-06

申请人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

发明人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.

摘要翻译： 在一个实施例中，半导体存储器件包括具有突出部分的半导体衬底，在至少一个突出半导体衬底部分上形成的隧道绝缘层，以及设置在隧道绝缘层上的浮动栅极结构。 浮动栅极结构的上部比浮动栅极结构的下部宽，并且浮动栅极结构的下部具有小于隧道绝缘层的宽度的宽度。 第一绝缘层部分形成在半导体衬底中并从半导体衬底突出，使得浮栅结构设置在突出的第一绝缘层部分之间。 在第一绝缘层部分和浮动栅极结构之上形成电介质层，并且在电介质层上形成控制栅极。

公开(公告)号：US08809932B2

公开(公告)日：2014-08-19

申请号：US11822548

申请日：2007-07-06

申请人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

发明人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.

摘要翻译： 在一个实施例中，半导体存储器件包括具有突出部分的半导体衬底，在至少一个突出半导体衬底部分上形成的隧道绝缘层，以及设置在隧道绝缘层上的浮动栅极结构。 浮动栅极结构的上部比浮动栅极结构的下部宽，并且浮动栅极结构的下部具有小于隧道绝缘层的宽度的宽度。 第一绝缘层部分形成在半导体衬底中并从半导体衬底突出，使得浮栅结构设置在突出的第一绝缘层部分之间。 在第一绝缘层部分和浮动栅极结构之上形成电介质层，并且在电介质层上形成控制栅极。

公开(公告)号：US08049269B2

公开(公告)日：2011-11-01

申请号：US11898266

申请日：2007-09-11

申请人： Se-Hoon Lee ,  Kyu-Charn Park ,  Jeong-Dong Choe

发明人： Se-Hoon Lee ,  Kyu-Charn Park ,  Jeong-Dong Choe

IPC分类号： H01L29/792 ,  H01L29/788 ,  H01L21/336 ,  H01L21/8247

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： In a non-volatile memory device, active fin structures extending in a first direction may be formed on a substrate. A tunnel insulating layer may be formed on surfaces of the active fin structures and bottom surfaces of trenches that may be defined by the active fin structures. A charge trapping layer and a blocking layer may be sequentially formed on the tunnel insulating layer. A gate electrode structure may include first portions disposed over top surfaces of the active fin structures and second portions vertically spaced apart from portions of the charge trapping layer that may be disposed over the bottom surfaces of the trenches, and may extend in a second direction substantially perpendicular to the first direction. Thus, lateral electron diffusion may be reduced in the charge trapping layer, and thereby the data retention performance and/or reliability of the non-volatile memory device may be improved.

摘要翻译： 在非易失性存储器件中，可以在衬底上形成沿第一方向延伸的活性鳍结构。 隧道绝缘层可以形成在活动鳍结构和沟槽底表面的表面上，沟槽绝缘层可以由活性鳍结构限定。 电荷俘获层和阻挡层可以顺序形成在隧道绝缘层上。 栅极电极结构可以包括设置在有源鳍结构的顶表面上的第一部分和与可以设置在沟槽的底表面之上的电荷俘获层的部分垂直间隔开的第二部分，并且可以在基本上 垂直于第一方向。 因此，电荷捕捉层中的横向电子扩散可能减少，从而可以提高非易失性存储器件的数据保持性能和/或可靠性。

公开(公告)号：US20080061361A1

公开(公告)日：2008-03-13

申请号：US11898266

申请日：2007-09-11

申请人： Se-Hoon Lee ,  Kyu-Charn Park ,  Jeong-Dong Choe

发明人： Se-Hoon Lee ,  Kyu-Charn Park ,  Jeong-Dong Choe

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： In a non-volatile memory device, active fin structures extending in a first direction may be formed on a substrate. A tunnel insulating layer may be formed on surfaces of the active fin structures and bottom surfaces of trenches that may be defined by the active fin structures. A charge trapping layer and a blocking layer may be sequentially formed on the tunnel insulating layer. A gate electrode structure may include first portions disposed over top surfaces of the active fin structures and second portions vertically spaced apart from portions of the charge trapping layer that may be disposed over the bottom surfaces of the trenches, and may extend in a second direction substantially perpendicular to the first direction. Thus, lateral electron diffusion may be reduced in the charge trapping layer, and thereby the data retention performance and/or reliability of the non-volatile memory device may be improved.

摘要翻译： 在非易失性存储器件中，可以在衬底上形成沿第一方向延伸的活性鳍结构。 隧道绝缘层可以形成在活动鳍结构和沟槽底表面的表面上，沟槽绝缘层可以由活性鳍结构限定。 电荷俘获层和阻挡层可以顺序形成在隧道绝缘层上。 栅极电极结构可以包括设置在有源鳍结构的顶表面上的第一部分和与可以设置在沟槽的底表面之上的电荷俘获层的部分垂直间隔开的第二部分，并且可以在基本上 垂直于第一方向。 因此，电荷捕捉层中的横向电子扩散可能减少，从而可以提高非易失性存储器件的数据保持性能和/或可靠性。

公开(公告)号：US20100020601A1

公开(公告)日：2010-01-28

申请号：US12471729

申请日：2009-05-26

申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C2211/5641

摘要： A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

摘要翻译： 非易失性存储器件包括被配置为支持单位和多位编程状态的非易失性存储器单元的阵列。 提供了一种控制电路，其被配置为在第一编程操作期间将阵列中的第一页非易失性存储单元编程为M位单元，并且还被配置为将第一页非易失性存储单元编程为N- 在第二次编程操作期间。 第一和第二编程操作通过至少一个擦除非易失性存储器单元的第一页的操作在时间上被分离。 M和N是不等于零的整数。

公开(公告)号：US08315102B2

公开(公告)日：2012-11-20

申请号：US13289689

申请日：2011-11-04

申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C2211/5641

摘要： A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

摘要翻译： 非易失性存储器件包括被配置为支持单位和多位编程状态的非易失性存储器单元的阵列。 提供了一种控制电路，其被配置为在第一编程操作期间将阵列中的第一页非易失性存储单元编程为M位单元，并且还被配置为将第一页非易失性存储单元编程为N- 在第二次编程操作期间。 第一和第二编程操作通过至少一个擦除非易失性存储器单元的第一页的操作在时间上被分离。 M和N是不等于零的整数。

公开(公告)号：US08059469B2

公开(公告)日：2011-11-15

申请号：US12481916

申请日：2009-06-10

申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jeong-Dong Choe ,  Tae-Yong Kim ,  Woo-Jung Kim ,  Dong-Hoon Jang ,  Young-Bae Yoon ,  Ki-Hyun Kim ,  Min-Tai Yu

发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jeong-Dong Choe ,  Tae-Yong Kim ,  Woo-Jung Kim ,  Dong-Hoon Jang ,  Young-Bae Yoon ,  Ki-Hyun Kim ,  Min-Tai Yu

IPC分类号： G11C11/34

CPC分类号： H01L27/11573 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L29/78

摘要： A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.

摘要翻译： 半导体器件包括限定在衬底中的驱动有源区和设置在驱动有源区的至少三个驱动晶体管。 驱动晶体管共享一个共同的源极/漏极，并且每个驱动晶体管包括彼此独立的各个源极/漏极。 公共源极/漏极和各个源极/漏极设置在驱动有源区域中。

公开(公告)号：US20100008152A1

公开(公告)日：2010-01-14

申请号：US12481916

申请日：2009-06-10

申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jeong-Dong Choe ,  Tae-Yong Kim ,  Woo-Jung Kim ,  Dong-Hoon Jang ,  Young-Bae Yoon ,  Ki-Hyun Kim ,  Min-Tai Yu

发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jeong-Dong Choe ,  Tae-Yong Kim ,  Woo-Jung Kim ,  Dong-Hoon Jang ,  Young-Bae Yoon ,  Ki-Hyun Kim ,  Min-Tai Yu

IPC分类号： G11C11/4096 ,  G11C5/06

CPC分类号： H01L27/11573 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L29/78

摘要： A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.

摘要翻译： 半导体器件包括限定在衬底中的驱动有源区和设置在驱动有源区的至少三个驱动晶体管。 驱动晶体管共享一个共同的源极/漏极，并且每个驱动晶体管包括彼此独立的各个源极/漏极。 公共源极/漏极和各个源极/漏极设置在驱动有源区域中。

公开(公告)号：US08072804B2

公开(公告)日：2011-12-06

申请号：US12471729

申请日：2009-05-26

申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C2211/5641

摘要： A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

摘要翻译： 非易失性存储器件包括被配置为支持单位和多位编程状态的非易失性存储器单元的阵列。 提供了一种控制电路，其被配置为在第一编程操作期间将阵列中的第一页非易失性存储单元编程为M位单元，并且还被配置为将第一页非易失性存储单元编程为N- 在第二次编程操作期间。 第一和第二编程操作通过至少一个擦除非易失性存储器单元的第一页的操作在时间上被分离。 M和N是不等于零的整数。

公开(公告)号：US08044908B2

公开(公告)日：2011-10-25

申请号：US12013151

申请日：2008-01-11

申请人： Se-Hoon Lee

发明人： Se-Hoon Lee

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/2092 ,  G09G2300/0417 ,  G09G2310/0289 ,  G09G2310/06 ,  G09G2320/0233 ,  G09G2330/02

摘要： A liquid crystal display device includes a timing controller generating a voltage compensation control pulse and a gate control signal, a voltage compensation signal generator generating a voltage compensation signal, the voltage level of which is gradually reduced during one frame period, in response to the voltage compensation control pulse, a power unit outputting a gate-on voltage to a plurality of gate lines by gradually increasing the level of the gate-on voltage in response to the voltage compensation signal, and a gate driver sequentially supplying the gate-on voltage to the plurality of gate lines in response to the gate control signal.

摘要翻译： 液晶显示装置包括产生电压补偿控制脉冲和栅极控制信号的定时控制器，产生电压补偿信号的电压补偿信号发生器，其电压电平在一个帧周期期间响应电压逐渐减小 补偿控制脉冲，功率单元，通过响应于电压补偿信号逐渐增加栅极导通电压的电平，向多条栅极线输出栅极导通电压，以及栅极驱动器，顺序地将栅极导通电压提供给 多个栅极线响应于栅极控制信号。