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公开(公告)号：US08502235B2
公开(公告)日：2013-08-06
申请号：US13010411
申请日：2011-01-20
IPC分类号： H01L29/12
CPC分类号： H03H9/0542 , H01L27/20 , H03H3/08 , H03H9/02228 , H03H9/02574 , H03H9/02976
摘要： A monolithic electronic device includes a first nitride epitaxial structure including a plurality of nitride epitaxial layers. The plurality of nitride epitaxial layers include at least one common nitride epitaxial layer. A second nitride epitaxial structure is on the common nitride epitaxial layer of the first nitride epitaxial structure. A first plurality of electrical contacts is on the first epitaxial nitride structure and defines a first electronic device in the first nitride epitaxial structure. A second plurality of electrical contacts is on the first epitaxial nitride structure and defines a second electronic device in the second nitride epitaxial structure. A monolithic electronic device includes a bulk semi-insulating silicon carbide substrate having implanted source and drain regions and an implanted channel region between the source and drain regions, and a nitride epitaxial structure on the surface of the silicon carbide substrate. Corresponding methods are also disclosed.
摘要翻译： 单片电子器件包括包括多个氮化物外延层的第一氮化物外延结构。 多个氮化物外延层包括至少一个共同的氮化物外延层。 第二氮化物外延结构在第一氮化物外延结构的公共氮化物外延层上。 第一多个电触点在第一外延氮化物结构上，并且限定第一氮化物外延结构中的第一电子器件。 第二多个电触点位于第一外延氮化物结构上，并且在第二氮化物外延结构中限定第二电子器件。 单片电子器件包括具有注入的源极和漏极区域以及源极和漏极区域之间的注入沟道区域以及在碳化硅衬底的表面上的氮化物外延结构的体半半绝缘碳化硅衬底。 还公开了相应的方法。
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公开(公告)号：US07875910B2
公开(公告)日：2011-01-25
申请号：US11410768
申请日：2006-04-25
IPC分类号： H01L29/80 , H01L21/338
CPC分类号： H03H9/0542 , H01L27/20 , H03H3/08 , H03H9/02228 , H03H9/02574 , H03H9/02976
摘要： A monolithic electronic device includes a first nitride epitaxial structure including a plurality of nitride epitaxial layers. The plurality of nitride epitaxial layers include at least one common nitride epitaxial layer. A second nitride epitaxial structure is on the common nitride epitaxial layer of the first nitride epitaxial structure. A first plurality of electrical contacts is on the first epitaxial nitride structure and defines a first electronic device in the first nitride epitaxial structure. A second plurality of electrical contacts is on the first epitaxial nitride structure and defines a second electronic device in the second nitride epitaxial structure. A monolithic electronic device includes a bulk semi-insulating silicon carbide substrate having implanted source and drain regions and an implanted channel region between the source and drain regions, and a nitride epitaxial structure on the surface of the silicon carbide substrate. Corresponding methods are also disclosed.
摘要翻译： 单片电子器件包括包括多个氮化物外延层的第一氮化物外延结构。 多个氮化物外延层包括至少一个共同的氮化物外延层。 第二氮化物外延结构在第一氮化物外延结构的公共氮化物外延层上。 第一多个电触点在第一外延氮化物结构上，并且限定第一氮化物外延结构中的第一电子器件。 第二多个电触点位于第一外延氮化物结构上，并且在第二氮化物外延结构中限定第二电子器件。 单片电子器件包括具有注入的源极和漏极区域以及源极和漏极区域之间的注入沟道区域的半体绝缘碳化硅衬底和在碳化硅衬底的表面上的氮化物外延结构。 还公开了相应的方法。
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公开(公告)号：US20110114968A1
公开(公告)日：2011-05-19
申请号：US13010411
申请日：2011-01-20
IPC分类号： H01L29/12
CPC分类号： H03H9/0542 , H01L27/20 , H03H3/08 , H03H9/02228 , H03H9/02574 , H03H9/02976
摘要： A monolithic electronic device includes a first nitride epitaxial structure including a plurality of nitride epitaxial layers. The plurality of nitride epitaxial layers include at least one common nitride epitaxial layer. A second nitride epitaxial structure is on the common nitride epitaxial layer of the first nitride epitaxial structure. A first plurality of electrical contacts is on the first epitaxial nitride structure and defines a first electronic device in the first nitride epitaxial structure. A second plurality of electrical contacts is on the first epitaxial nitride structure and defines a second electronic device in the second nitride epitaxial structure. A monolithic electronic device includes a bulk semi-insulating silicon carbide substrate having implanted source and drain regions and an implanted channel region between the source and drain regions, and a nitride epitaxial structure on the surface of the silicon carbide substrate. Corresponding methods are also disclosed.
摘要翻译： 单片电子器件包括包括多个氮化物外延层的第一氮化物外延结构。 多个氮化物外延层包括至少一个共同的氮化物外延层。 第二氮化物外延结构在第一氮化物外延结构的公共氮化物外延层上。 第一多个电触点在第一外延氮化物结构上，并且限定第一氮化物外延结构中的第一电子器件。 第二多个电触点位于第一外延氮化物结构上，并且在第二氮化物外延结构中限定第二电子器件。 单片电子器件包括具有注入的源极和漏极区域以及源极和漏极区域之间的注入沟道区域的半体绝缘碳化硅衬底和在碳化硅衬底的表面上的氮化物外延结构。 还公开了相应的方法。
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公开(公告)号：US08575651B2
公开(公告)日：2013-11-05
申请号：US11103117
申请日：2005-04-11
申请人： Adam William Saxler , Yifeng Wu , Primit Parikh , Umesh Mishra , Richard Peter Smith , Scott T. Sheppard
发明人： Adam William Saxler , Yifeng Wu , Primit Parikh , Umesh Mishra , Richard Peter Smith , Scott T. Sheppard
IPC分类号： H01L31/072
CPC分类号： H01L21/0254 , H01L21/0237 , H01L21/02425 , H01L21/02439 , H01L21/02491 , H01L21/02581 , H01L21/0262 , H01L29/1608 , H01L29/2003 , H01L29/4175 , H01L29/41766 , H01L29/66462 , H01L29/7787
摘要： Semiconductor device structures and methods of fabricating semiconductor devices structures are provided that include a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate and/or a conductive layer. The semi-insulating or insulating GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive SiC substrate and an insulating or semi-insulating GaN epitaxial layer on the conductive SiC substrate. The GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive GaN substrate, an insulating or semi-insulating GaN epitaxial layer on the conductive GaN substrate, a GaN based semiconductor device on the GaN epitaxial layer and a via hole and corresponding via metal in the via hole that extends through layers of the GaN based semiconductor device and the GaN epitaxial layer.
摘要翻译： 提供半导体器件结构和制造半导体器件结构的方法，其包括在导电半导体衬底和/或导电层上的半绝缘或绝缘GaN外延层。 半绝缘或绝缘GaN外延层具有至少约4μm的厚度。 还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括在导电SiC衬底上的导电SiC衬底和绝缘或半绝缘GaN外延层。 GaN外延层具有至少约4μm的厚度。 还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括导电GaN衬底，导电GaN衬底上的绝缘或半绝缘GaN外延层，GaN外延层上的GaN基半导体器件和 通孔和通孔中相应的通孔金属延伸穿过GaN基半导体器件和GaN外延层的层。
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5.发明授权Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses 有权基于氮化物的晶体管及其使用非蚀刻接触凹槽的制造方法公开(公告)号：US07550784B2
公开(公告)日：2009-06-23
申请号：US11221343
申请日：2005-09-07
IPC分类号： H01L29/775
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/7787
摘要： Contacts for a nitride based transistor and methods of fabricating such contacts provide a recess through a regrowth process. The contacts are formed in the recess. The regrowth process includes fabricating a first cap layer comprising a Group III-nitride semiconductor material. A mask is fabricated and patterned on the first cap layer. The pattern of the mask corresponds to the pattern of the recesses for the contacts. A second cap layer comprising a Group III-nitride semiconductor material is selectively fabricated (e.g. grown) on the first cap layer utilizing the patterned mask. Additional layers may also be formed on the second cap layer. The mask may be removed to provide recess(es) to the first cap layer, and contact(s) may be formed in the recess(es). Alternatively, the mask may comprise a conductive material upon which a contact may be formed, and may not require removal.
摘要翻译： 用于氮化物基晶体管的触点和制造这种触点的方法通过再生长工艺提供凹陷。 触点形成在凹部中。 再生过程包括制造包含III族氮化物半导体材料的第一盖层。 在第一盖层上制造和图案化掩模。 掩模的图案对应于用于触点的凹部的图案。 使用图案化掩模，在第一盖层上选择性地制造（例如，生长）包含III族氮化物半导体材料的第二盖层。 另外的层也可以形成在第二盖层上。 可以去除掩模以向第一盖层提供凹部，并且可以在凹部中形成接触。 或者，掩模可以包括导电材料，可以在其上形成接触，并且可以不需要去除。
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6.发明授权Group III nitride semiconductor devices with silicon nitride layers and methods of manufacturing such devices 有权具有氮化硅层的III族氮化物半导体器件及其制造方法公开(公告)号：US08481376B2
公开(公告)日：2013-07-09
申请号：US13010053
申请日：2011-01-20
IPC分类号： H01L21/338
CPC分类号： H01L29/7783 , H01L29/2003 , H01L29/66462
摘要： Methods of fabricating transistor in which a first Group III nitride layer is formed on a substrate in a reactor, and a second Group III nitride layer is formed on the first Group III nitride layer. An insulating layer such as, for example, a silicon nitride layer is formed on the second Group III nitride layer in-situ in the reactor. The substrate including the first Group III nitride layer, the second group III nitride layer and the silicon nitride layer is removed from the reactor, and the silicon nitride layer is patterned to form a first contact hole that exposes a first contact region of the second Group III nitride layer. A metal contact is formed on the first contact region of the second Group III nitride layer.
摘要翻译： 在第一III族氮化物层上形成制造其中在反应器中的基板上形成第一III族氮化物层的晶体管和第二III族氮化物层的方法。 在反应器中原位形成第二III族氮化物层等绝缘层，例如氮化硅层。 从反应器中除去包括第一III族氮化物层，第二III族氮化物层和氮化硅层的衬底，并对该氮化硅层进行构图以形成暴露第二组的第一接触区域的第一接触孔 III族氮化物层。 在第二III族氮化物层的第一接触区域上形成金属接触。
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公开(公告)号：US07709859B2
公开(公告)日：2010-05-04
申请号：US11684747
申请日：2007-03-12
IPC分类号： H01L29/84 , H01L21/338
CPC分类号： H01L29/66462 , H01L21/318 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/7786 , H01L29/7787 , H01L2924/0002 , H01L2924/00
摘要： High electron mobility transistors are provided that include a non-uniform aluminum concentration AlGaN based cap layer having a high aluminum concentration adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. High electron mobility transistors are provided that include a cap layer having a doped region adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. Graphitic BN passivation structures for wide bandgap semiconductor devices are provided. SiC passivation structures for Group III-nitride semiconductor devices are provided. Oxygen anneals of passivation structures are also provided. Ohmic contacts without a recess are also provided.
摘要翻译： 提供了高电子迁移率晶体管，其包括与盖层的表面相邻的具有高铝浓度的不均匀的铝浓度的AlGaN基覆盖层，其远离设置有盖层的阻挡层。 提供了高电子迁移率晶体管，其包括具有邻近盖层的表面的掺杂区域的帽层，其远离其上设置盖层的阻挡层。 提供了宽带隙半导体器件的石墨BN钝化结构。 提供了III族氮化物半导体器件的SiC钝化结构。 还提供了钝化结构的氧气退火。 还提供了没有凹槽的欧姆接触。
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8.发明申请Group III nitride semiconductor devices with silicon nitride layers and methods of manufacturing such devices 有权具有氮化硅层的III族氮化物半导体器件及其制造方法公开(公告)号：US20100068855A1
公开(公告)日：2010-03-18
申请号：US11286805
申请日：2005-11-23
IPC分类号： H01L21/335 , H01L21/20
CPC分类号： H01L29/7783 , H01L29/2003 , H01L29/66462
摘要： Methods of fabricating transistor in which a first Group III nitride layer is formed on a substrate in a reactor, and a second Group III nitride layer is formed on the first Group III nitride layer. An insulating layer such as, for example, a silicon nitride layer is formed on the second Group III nitride layer in-situ in the reactor. The substrate including the first Group III nitride layer, the second group III nitride layer and the silicon nitride layer is removed from the reactor, and the silicon nitride layer is patterned to form a first contact hole that exposes a first contact region of the second Group III nitride layer. A metal contact is formed on the first contact region of the second Group III nitride layer.
摘要翻译： 在第一III族氮化物层上形成制造其中在反应器中的基板上形成第一III族氮化物层的晶体管和第二III族氮化物层的方法。 在反应器中原位形成第二III族氮化物层等绝缘层，例如氮化硅层。 从反应器中除去包括第一III族氮化物层，第二III族氮化物层和氮化硅层的衬底，并对该氮化硅层进行构图以形成暴露第二组的第一接触区域的第一接触孔 III族氮化物层。 在第二III族氮化物层的第一接触区域上形成金属接触。
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9.发明申请Group III Nitride Field Effect Transistors (FETS) Capable of Withstanding High Temperature Reverse Bias Test Conditions 有权第III组氮化物场效应晶体管（FETS）能承受高温反向偏压测试条件公开(公告)号：US20090101939A1
公开(公告)日：2009-04-23
申请号：US12270063
申请日：2008-11-13
IPC分类号： H01L29/78
CPC分类号： H01L27/0605 , H01L29/2003 , H01L29/207 , H01L29/42316 , H01L29/7787
摘要： Group III Nitride based field effect transistor (FETs) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (VDS) of about from about 28 to about 70 volts, a gate to source voltage (Vgs) of from about −3.3 to about −14 volts and a normal operating temperature for at least about 10 hours.
摘要翻译： 提供基于III族氮化物的场效应晶体管（FET），其在约28至约70伏特的漏极 - 源极电压（VDS）下操作时具有小于约3.0dB的功率劣化，栅极至源极电压 （Vgs）为约-3.3至约-14伏，正常工作温度为至少约10小时。
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10.发明授权Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions 有权能耐受高温反向偏压测试条件的III类氮化物场效应晶体管（FETS）公开(公告)号：US08803198B2
公开(公告)日：2014-08-12
申请号：US13483607
申请日：2012-05-30
IPC分类号： H01L29/739 , H01L31/072
CPC分类号： H01L27/0605 , H01L29/2003 , H01L29/207 , H01L29/42316 , H01L29/7787
摘要： Group III Nitride based field effect transistor (FETs) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (VDS) of about from about 28 to about 70 volts, a gate to source voltage (Vgs) of from about −3.3 to about −14 volts and a normal operating temperature for at least about 10 hours.
摘要翻译： 提供基于III族氮化物的场效应晶体管（FET），其在约28至约70伏特的漏极 - 源极电压（VDS）下操作时具有小于约3.0dB的功率劣化，栅极至源极电压 （Vgs）为约-3.3至约-14伏，正常工作温度为至少约10小时。
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