公开(公告)号：US11410994B2

公开(公告)日：2022-08-09

申请号：US17024044

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah Nam ,  Byungju Kang ,  Byungsung Kim ,  Hyelim Kim ,  Sungho Park ,  Yubo Qian

IPC: H01L27/088 ,  H01L23/538 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/02 ,  H01L29/775 ,  H01L29/78

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US11908855B2

公开(公告)日：2024-02-20

申请号：US17880819

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah Nam ,  Byungju Kang ,  Byungsung Kim ,  Hyelim Kim ,  Sungho Park ,  Yubo Qian

IPC: H01L27/088 ,  H01L23/538 ,  H01L29/06 ,  H01L29/423 ,  B82Y10/00 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/02 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L23/5384 ,  H01L29/0653 ,  H01L29/4232

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20190148292A1

公开(公告)日：2019-05-16

申请号：US16244137

申请日：2019-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yubo Qian ,  Byung Sung Kim ,  Hyeon Uk Kim ,  Young Gook Park ,  Chul Hong Park

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device includes a first conductive element, a first insulating layer and a second insulating layer sequentially disposed on the first conductive element, a conductive via passing through the first insulating layer and the second insulating layer. The conductive via is connected to the first conductive element. The semiconductor device includes a via extension portion disposed in the second insulating layer that extends along an upper surface of the first insulating layer from one side surface of the conductive via, and a second conductive element disposed on the second insulating layer that is connected to the via extension portion.

公开(公告)号：US10217705B1

公开(公告)日：2019-02-26

申请号：US15894968

申请日：2018-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yubo Qian ,  Byung Sung Kim ,  Hyeon Uk Kim ,  Young Gook Park ,  Chul Hong Park

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a first conductive element, a first insulating layer and a second insulating layer sequentially disposed on the first conductive element, a conductive via passing through the first insulating layer and the second insulating layer. The conductive via is connected to the first conductive element. The semiconductor device includes a via extension portion disposed in the second insulating layer that extends along an upper surface of the first insulating layer from one side surface of the conductive via, and a second conductive element disposed on the second insulating layer that is connected to the via extension portion.

公开(公告)号：US12261171B2

公开(公告)日：2025-03-25

申请号：US18416375

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah Nam ,  Byungju Kang ,  Byungsung Kim ,  Hyelim Kim ,  Sungho Park ,  Yubo Qian

IPC: H01L27/088 ,  B82Y10/00 ,  H01L21/8234 ,  H01L23/538 ,  H01L27/02 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20240421082A1

公开(公告)日：2024-12-19

申请号：US18662042

申请日：2024-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeon Won Jeong ,  Yubo Qian ,  Sutae Kim ,  Jae Young Park ,  Jin Woo Lee

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including a standard cell area and an ending cell area that at least partially surrounds the standard cell area; a first active pattern in the standard cell area; a first wiring that extends in a first direction and is on the first active pattern; a first gate electrode that extends in a second direction and is on the first active pattern; a first gate contact; a second active pattern in the ending cell area; a second wiring that extends in the first direction and is on the second active pattern; a second gate electrode that extends in the second direction and is on the second active pattern; and a second gate contact.

公开(公告)号：US10403619B2

公开(公告)日：2019-09-03

申请号：US15787244

申请日：2017-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yubo Qian ,  Byung-Sung Kim ,  Chul-Hong Park ,  Haewang Lee

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/522 ,  G06F17/50 ,  H01L21/8238 ,  H01L27/092 ,  H03K19/0948 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes first and second logic cells adjacent to each other in a first direction on a substrate, a gate electrode extending in the first direction in each of the first and second logic cells, a power line extending in a second direction at a boundary between the first and second logic cells, and a connection structure electrically connecting the power line to an active pattern of the first logic cell and to an active pattern of the second logic cell. The connection structure lies below the power line and extends from the first logic cell to the second logic cell. A top surface of the connection structure is at a higher level than that of a top surface of the gate electrode.

公开(公告)号：US20190043804A1

公开(公告)日：2019-02-07

申请号：US15894968

申请日：2018-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yubo Qian ,  Byung Sung Kim ,  Hyeon Uk Kim ,  Young Gook Park ,  Chul Hong Park

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a first conductive element, a first insulating layer and a second insulating layer sequentially disposed on the first conductive element, a conductive via passing through the first insulating layer and the second insulating layer. The conductive via is connected to the first conductive element. The semiconductor device includes a via extension portion disposed in the second insulating layer that extends along an upper surface of the first insulating layer from one side surface of the conductive via, and a second conductive element disposed on the second insulating layer that is connected to the via extension portion.