公开(公告)号：US20230353132A1

公开(公告)日：2023-11-02

申请号：US18219254

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mingyu LEE ,  Youngchul CHO ,  Seungjin PARK ,  Youngdon CHOI ,  Junghwan CHOI

IPC: H03K5/06 ,  H03K5/05 ,  H03K5/15

CPC classification number: H03K5/06 ,  H03K5/05 ,  H03K5/1506 ,  H03K5/1508

Abstract: A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

公开(公告)号：US20230072675A1

公开(公告)日：2023-03-09

申请号：US17695168

申请日：2022-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mingyu LEE ,  Youngchul CHO ,  Seungjin PARK ,  Youngdon CHOI ,  Junghwan CHOI

IPC: H03K5/06 ,  H03K5/15 ,  H03K5/05

Abstract: A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

公开(公告)号：US20240248207A1

公开(公告)日：2024-07-25

申请号：US18587480

申请日：2024-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngchul CHO ,  Jungwoo KIM ,  Tatsuhiro OTSUKA

IPC: G01S17/04 ,  G01S7/481 ,  G01S17/42 ,  G02B5/09 ,  G02B26/12 ,  G02B27/09

CPC classification number: G01S17/04 ,  G01S7/4817 ,  G01S17/42 ,  G02B5/09 ,  G02B26/121 ,  G02B27/0972

Abstract: An optical scanner includes at least one light source configured to emit light, a steering unit configured to perform scanning in a first direction based on the light emitted from the at least one light source, and a polygon mirror configured to perform, by using the light output from the steering unit, scanning in a second direction different than the first direction based on a rotation of the polygon mirror. The steering unit includes a plurality of first prisms, and each of the plurality of first prisms includes an incident facet configured to pass the light emitted from the at least one light source, and an output facet configured to refract and output the light. The polygon mirror includes a plurality of reflective facets, and each of the plurality of reflective facets is configured to that reflect the light output from the steering unit.

公开(公告)号：US20230410917A1

公开(公告)日：2023-12-21

申请号：US18100173

申请日：2023-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hojun YOON ,  Jinha HWANG ,  Seunghoon LEE ,  Youngchul CHO ,  Youngdon CHOI ,  Junghwan CHOI

IPC: G11C16/30 ,  G11C16/24

CPC classification number: G11C16/30 ,  G11C16/24

Abstract: An input/output circuit of a nonvolatile memory device and a nonvolatile memory device. The input/output circuit of a nonvolatile memory device includes a driver, which is configured to output data from the nonvolatile memory device to a data line, and a power gating circuit, which is connected between the driver and a power terminal or between the driver and a ground terminal and configured to block a leakage current of the driver. The power gating circuit includes a plurality of transistors electrically connected in parallel and having threshold voltages of different magnitudes, respectively.

公开(公告)号：US20240221795A1

公开(公告)日：2024-07-04

申请号：US18231935

申请日：2023-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngwoo PARK ,  Tongsung KIM ,  Youngmin KIM ,  Seungjin PARK ,  Seunghoon LEE ,  Chaekang LIM ,  Youngchul CHO ,  Youngdon CHOI ,  Junghwan CHOI

IPC: G11C7/10 ,  H03F3/45 ,  H03K5/24 ,  H03M1/06

CPC classification number: G11C7/1048 ,  H03F3/45475 ,  H03K5/24 ,  H03M1/0607 ,  H03F2200/375 ,  H03F2203/45044 ,  H03F2203/45212

Abstract: A data converter including an autozeroing circuit including a plurality of gain circuits having a first amplification circuit and a first capacitor connected to the first amplification circuit, the first amplification circuit performing a switch feedthrough offset cancellation operation of storing an offset voltage of the autozeroing circuit in the capacitor through a switch, a comparator circuit including a first input terminal and a second input terminal, the comparator circuit comparing a first input terminal voltage level of the first input terminal with a second input terminal voltage level of the second input terminal, a first switch unit connected between the autozeroing circuit and the comparator circuit, the first switch disconnecting the autozeroing circuit from the comparator circuit during the switch feedthrough offset cancellation operation of the autozeroing circuit, and a second switch unit connected between a first input signal line and a second input signal line.

公开(公告)号：US20230170003A1

公开(公告)日：2023-06-01

申请号：US18046030

申请日：2022-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Baek Jin LIM ,  Youngchul CHO ,  Seungjin PARK ,  Doobock LEE ,  Youngdon CHOI ,  Junghwan CHOI

IPC: G11C7/10 ,  G11C8/10 ,  H03K19/0175 ,  G11C7/04

CPC classification number: G11C7/1063 ,  G11C8/10 ,  H03K19/017545 ,  G11C7/1036 ,  G11C7/04 ,  G11C2207/2254

Abstract: There is provided a semiconductor device, which includes a calibration code generator circuit configured to generate a calibration code according to changes in external conditions, a first driver circuit configured to output a data signal with an impedance value controlled by the calibration code, an emphasis control circuit configured to generate an emphasis data signal using the data signal, and to change the calibration code according to an operating frequency to generate an emphasis code; and a second driver circuit configured to output the emphasis data signal with an impedance value controlled by the emphasis code.

公开(公告)号：US20220209729A1

公开(公告)日：2022-06-30

申请号：US17536064

申请日：2021-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baekjin LIM ,  Youngchul CHO ,  Seungjin PARK ,  Youngdon CHOI ,  Junghwan CHOI

IPC: H03F3/45

Abstract: An amplifier circuit comprises a first unit circuit and a second unit circuit. The first unit circuit may include a first current mirror circuit that includes a first active inductor including a P-channel transistor, and a first input circuit configured to generate a first differential current and a second differential current based on a pair of differential input signals. The second unit circuit may include a second current mirror circuit that includes a second active inductor including a P-channel transistor, and a second input circuit configured to generate a third differential current and a fourth differential current based on the pair of differential input signals.