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公开(公告)号：US20240231858A1
公开(公告)日：2024-07-11
申请号：US18613691
申请日：2024-03-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangsub BYUN , Seungjin PARK
Abstract: A display apparatus is provided. The display apparatus includes a display and a processor configured to count time for operating a screen saver after a user input is received, and based on the counted time corresponding to a threshold time, control the display to display a screen corresponding to the screen saver by operating the screen saver.
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2.发明公开公开(公告)号：US20240170085A1
公开(公告)日：2024-05-23
申请号：US18200709
申请日：2023-05-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hojun YOON , Youngdon CHOI , Seungjin PARK , Seunghoon LEE , Junghwan CHOI
CPC classification number: G11C29/12015 , G11C7/222 , G11C8/18 , H03K5/1565
Abstract: A semiconductor device has a memory controller configured to provide a data strobe signal, and a memory device configured to receive a data signal provided from the memory controller or output a data signal to the memory controller, wherein the memory device includes a memory interface including a plurality of DQ driving circuits, the memory interface being configured to generate a plurality of phase clock signals based on the data strobe signal, determine a number of phase clock signals provided to the plurality of DQ driving circuits based on an operating frequency of the memory device, and provide the determined number of phase clock signals to the plurality of DQ driving circuits.
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公开(公告)号：US20230072675A1
公开(公告)日：2023-03-09
申请号：US17695168
申请日：2022-03-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Mingyu LEE , Youngchul CHO , Seungjin PARK , Youngdon CHOI , Junghwan CHOI
Abstract: A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.
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Patent Agency Ranking
公开(公告)号：US20230353132A1
公开(公告)日：2023-11-02
申请号：US18219254
申请日：2023-07-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Mingyu LEE , Youngchul CHO , Seungjin PARK , Youngdon CHOI , Junghwan CHOI
CPC classification number: H03K5/06 , H03K5/05 , H03K5/1506 , H03K5/1508
Abstract: A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.
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公开(公告)号：US20240221795A1
公开(公告)日：2024-07-04
申请号：US18231935
申请日：2023-08-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngwoo PARK , Tongsung KIM , Youngmin KIM , Seungjin PARK , Seunghoon LEE , Chaekang LIM , Youngchul CHO , Youngdon CHOI , Junghwan CHOI
CPC classification number: G11C7/1048 , H03F3/45475 , H03K5/24 , H03M1/0607 , H03F2200/375 , H03F2203/45044 , H03F2203/45212
Abstract: A data converter including an autozeroing circuit including a plurality of gain circuits having a first amplification circuit and a first capacitor connected to the first amplification circuit, the first amplification circuit performing a switch feedthrough offset cancellation operation of storing an offset voltage of the autozeroing circuit in the capacitor through a switch, a comparator circuit including a first input terminal and a second input terminal, the comparator circuit comparing a first input terminal voltage level of the first input terminal with a second input terminal voltage level of the second input terminal, a first switch unit connected between the autozeroing circuit and the comparator circuit, the first switch disconnecting the autozeroing circuit from the comparator circuit during the switch feedthrough offset cancellation operation of the autozeroing circuit, and a second switch unit connected between a first input signal line and a second input signal line.
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公开(公告)号：US20230170003A1
公开(公告)日：2023-06-01
申请号：US18046030
申请日：2022-10-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Baek Jin LIM , Youngchul CHO , Seungjin PARK , Doobock LEE , Youngdon CHOI , Junghwan CHOI
IPC: G11C7/10 , G11C8/10 , H03K19/0175 , G11C7/04
CPC classification number: G11C7/1063 , G11C8/10 , H03K19/017545 , G11C7/1036 , G11C7/04 , G11C2207/2254
Abstract: There is provided a semiconductor device, which includes a calibration code generator circuit configured to generate a calibration code according to changes in external conditions, a first driver circuit configured to output a data signal with an impedance value controlled by the calibration code, an emphasis control circuit configured to generate an emphasis data signal using the data signal, and to change the calibration code according to an operating frequency to generate an emphasis code; and a second driver circuit configured to output the emphasis data signal with an impedance value controlled by the emphasis code.
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公开(公告)号：US20220209729A1
公开(公告)日：2022-06-30
申请号：US17536064
申请日：2021-11-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Baekjin LIM , Youngchul CHO , Seungjin PARK , Youngdon CHOI , Junghwan CHOI
IPC: H03F3/45
Abstract: An amplifier circuit comprises a first unit circuit and a second unit circuit. The first unit circuit may include a first current mirror circuit that includes a first active inductor including a P-channel transistor, and a first input circuit configured to generate a first differential current and a second differential current based on a pair of differential input signals. The second unit circuit may include a second current mirror circuit that includes a second active inductor including a P-channel transistor, and a second input circuit configured to generate a third differential current and a fourth differential current based on the pair of differential input signals.
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公开(公告)号：US20210185267A1
公开(公告)日：2021-06-17
申请号：US17119329
申请日：2020-12-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taehwan KIM , Sungjin SON , Seungjin PARK , Kwangsub BYUN , Junghwan CHOI , Byungkwon KANG , Seokjae LEE
IPC: H04N5/445 , H04N21/431
Abstract: Provided are a display apparatus and an operation method thereof for preventing image flicker when displaying mixed images: generating a first image corresponding to video content on a first plane, generating, on a second plane, a second image, outputting a mixed image that is a mixture of the first image and the second image, generating a third image on a third plane corresponding to the mixed image, and displaying the third image based on removal of the first image from the display.
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