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公开(公告)号：US20240211210A1
公开(公告)日：2024-06-27
申请号：US18331310
申请日：2023-06-08
Inventor： Jaerok KIM , Yoonmyung LEE
IPC: G06F7/544 , G11C11/418 , G11C11/419
CPC classification number: G06F7/5443 , G11C11/418 , G11C11/419
Abstract: An apparatus and method with in-memory computing (IMC) is provided. An apparatus includes a memory including rows; a self-timed circuit including sub-circuits corresponding to the respective rows, and operates asynchronously with a clock; and a control circuit configured to control the self-timed circuit. Based on input to a first sub-circuit being a first value, the first sub-circuit skips accessing a first row of memory, corresponding to the first sub-circuit and transfer a first output signal received from a first neighboring sub-circuit, to a second neighboring sub-circuit among the sub-circuits. Based on input to the first sub-circuit being a second value, the first sub-circuit accesses the first row of memory, performs an operator-based operation on the second value and weights stored in the first row, generates a second output signal based on the performed operation, and transfers the second output signal to the second neighboring sub-circuit.
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公开(公告)号：US20250149085A1
公开(公告)日：2025-05-08
申请号：US19011861
申请日：2025-01-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-Hoon CHUN , Jiho SONG , Yoonmyung LEE , Jua LEE
Abstract: A device with a neural network includes: a synaptic memory cell comprising a resistive memory element, which is disposed along an output line and which has either one of a first resistance value and a second resistance value, and configured to generate a column signal based on the resistive memory element and an input signal in response to the input signal being received through an input line; a reference memory cell comprising a reference memory element, which is disposed along a reference line and which has the second resistance value different from the first resistance value, and configured to generate a reference signal based on the reference memory element and the input signal; and an output circuit configured to generate an output signal for the output line from the column signal and the reference signal.
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公开(公告)号：US20230186986A1
公开(公告)日：2023-06-15
申请号：US17830004
申请日：2022-06-01
Inventor： Jung-Hoon CHUN , Jiho SONG , Yoonmyung LEE , Jua LEE
CPC classification number: G11C13/004 , G11C13/0069 , G11C13/0038 , G11C11/54
Abstract: A device with a neural network includes: a synaptic memory cell comprising a resistive memory element, which is disposed along an output line and which has either one of a first resistance value and a second resistance value, and configured to generate a column signal based on the resistive memory element and an input signal in response to the input signal being received through an input line; a reference memory cell comprising a reference memory element, which is disposed along a reference line and which has the second resistance value different from the first resistance value, and configured to generate a reference signal based on the reference memory element and the input signal; and an output circuit configured to generate an output signal for the output line from the column signal and the reference signal.
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公开(公告)号：US20220107661A1
公开(公告)日：2022-04-07
申请号：US17200017
申请日：2021-03-12
Inventor： Chisung BAE , Hyungmin GI , Yeohoon YOON , Yoonmyung LEE
Abstract: An apparatus and method for tracking maximum power are disclosed. The apparatus is configured to track a maximum power at a certain node of an electronic circuit, adjust an impedance of the electronic circuit such that power at the node is maximal, and adjust an impedance of the electronic circuit by comparing power at two points in time to increase power. The apparatus for tracking a maximum power, includes a charge sharing capacitor connected to an initial capacitor in parallel, a first switch disposed between the initial capacitor and an energy harvesting power supply, a second switch disposed between the initial capacitor and the charge sharing capacitor, a third switch disposed between the energy harvesting power supply and a comparator, and a switched-capacitor power converting circuit configured to control the initial capacitor.
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Patent Agency Ranking
公开(公告)号：US20200382000A1
公开(公告)日：2020-12-03
申请号：US16678021
申请日：2019-11-08
Inventor： Seungchul JUNG , Sang Joon KIM , Junyoung PARK , Yoonmyung LEE , Hyungmin GI
Abstract: A boost converter and a cell applicable to the boost converter are provided. The cell comprises a control circuit configured to generate a bottom control signal related to a bottom plate of a capacitor, and a top control signal related to a top plate of the capacitor to connect the capacitor based on one or more operational phases, and a booster configured to convert the top control signal generated by the control circuit, wherein the capacitor is configured to be sequentially connected to voltage levels through switches, based on the bottom control signal and the converted top control signal.
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公开(公告)号：US20230053948A1
公开(公告)日：2023-02-23
申请号：US17674134
申请日：2022-02-17
Inventor： Yoonmyung LEE , Soyoun JEONG , Jaerok KIM
IPC: G06F7/544
Abstract: A multiply-accumulator (MAC) circuit includes: a plurality of multipliers each comprising: a field-effect transistor configured to apply an intermediate voltage to a node; a pair of resistive devices having resistance values determined based on the intermediate voltage applied to one ends connected to the node and weight setting voltages applied to the other ends; and a capacitor configured to be charged and discharged with an electric charge by receiving a voltage generated in the node based on a combined resistance value of the pair of resistive devices and input voltages applied individually to the other ends of the pair of resistive devices in response to individual resistance values of the pair of resistive devices being determined; and an output line configured to output a voltage based on electric charges charged to and discharged from the plurality of multipliers.
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公开(公告)号：US20190386615A1
公开(公告)日：2019-12-19
申请号：US16268676
申请日：2019-02-06
Inventor： Jonghan KIM , Chisung BAE , Jaemin CHOI , Yoonmyung LEE , Jung-Hoon CHUN
IPC: H03B5/24
Abstract: An oscillator includes a constant current generator configured to generate a constant current by maintaining a predetermined potential difference between both a first end and a second end of a resistor, and an oscillating element configured to output a clock signal corresponding to a charge and discharge cycle of a capacitor based on a bias current corresponding to the constant current.
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公开(公告)号：US20240232595A1
公开(公告)日：2024-07-11
申请号：US18334516
申请日：2023-06-14
Inventor： Jung-Hoon CHUN , Jiho SONG , Yoonmyung LEE , Jua LEE
IPC: G06N3/063
CPC classification number: G06N3/063
Abstract: An electronic device with neural network circuitry is provided. The neural network circuit includes a synaptic memory cell including a memory element disposed along an output line and configured to, dependent on the memory element and an input signal applied to an input line, generate a column signal on the output line; a reference memory cell comprising a reference memory element disposed along a reference line, and configured to, dependent on the reference memory element and the input signal, generate a reference signal on the reference line; and a first neuron circuit configured to generate an output signal based on the column signal and the reference signal, and determine a start voltage of an integration to be performed based on the output signal in response to a previous firing by the first neuron circuit with respect to a previous input signal or another firing performed by a second neuron circuit.
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公开(公告)号：US20230298663A1
公开(公告)日：2023-09-21
申请号：US17883546
申请日：2022-08-08
Inventor： Jung Hoon CHUN , Ji Ho SONG , Yoonmyung LEE , Ju A LEE
CPC classification number: G11C11/54 , G11C13/004 , G06N3/061
Abstract: A neural network method and device are included, A neural network circuit includes a synaptic memory cell including a resistive memory element, which is disposed along an output line and which can have a first resistance value and a second resistance value as a resistance value, the synaptic memory cell generates a column signal, based on the resistance value of the resistive memory element and an input signal received via an input line, a reference memory cell including a reference memory element, which is disposed along a reference line and which has a resistance value that is a ratio of the first and second resistance values, the reference memory cell generates a reference signal, based on the resistance value of the reference memory element and the input signal, and an output circuit generates an output signal for the output line based on the column signal and the reference signal.
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