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公开(公告)号：US20240232595A1
公开(公告)日：2024-07-11
申请号：US18334516
申请日：2023-06-14
Inventor： Jung-Hoon CHUN , Jiho SONG , Yoonmyung LEE , Jua LEE
IPC: G06N3/063
CPC classification number: G06N3/063
Abstract: An electronic device with neural network circuitry is provided. The neural network circuit includes a synaptic memory cell including a memory element disposed along an output line and configured to, dependent on the memory element and an input signal applied to an input line, generate a column signal on the output line; a reference memory cell comprising a reference memory element disposed along a reference line, and configured to, dependent on the reference memory element and the input signal, generate a reference signal on the reference line; and a first neuron circuit configured to generate an output signal based on the column signal and the reference signal, and determine a start voltage of an integration to be performed based on the output signal in response to a previous firing by the first neuron circuit with respect to a previous input signal or another firing performed by a second neuron circuit.
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公开(公告)号：US20250149085A1
公开(公告)日：2025-05-08
申请号：US19011861
申请日：2025-01-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-Hoon CHUN , Jiho SONG , Yoonmyung LEE , Jua LEE
Abstract: A device with a neural network includes: a synaptic memory cell comprising a resistive memory element, which is disposed along an output line and which has either one of a first resistance value and a second resistance value, and configured to generate a column signal based on the resistive memory element and an input signal in response to the input signal being received through an input line; a reference memory cell comprising a reference memory element, which is disposed along a reference line and which has the second resistance value different from the first resistance value, and configured to generate a reference signal based on the reference memory element and the input signal; and an output circuit configured to generate an output signal for the output line from the column signal and the reference signal.
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公开(公告)号：US20230186986A1
公开(公告)日：2023-06-15
申请号：US17830004
申请日：2022-06-01
Inventor： Jung-Hoon CHUN , Jiho SONG , Yoonmyung LEE , Jua LEE
CPC classification number: G11C13/004 , G11C13/0069 , G11C13/0038 , G11C11/54
Abstract: A device with a neural network includes: a synaptic memory cell comprising a resistive memory element, which is disposed along an output line and which has either one of a first resistance value and a second resistance value, and configured to generate a column signal based on the resistive memory element and an input signal in response to the input signal being received through an input line; a reference memory cell comprising a reference memory element, which is disposed along a reference line and which has the second resistance value different from the first resistance value, and configured to generate a reference signal based on the reference memory element and the input signal; and an output circuit configured to generate an output signal for the output line from the column signal and the reference signal.
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