CDS CIRCUIT, OPERATING METHOD THEREOF, AND IMAGE SENSOR INCLUDING CDS CIRCUIT

    公开(公告)号:US20230007205A1

    公开(公告)日:2023-01-05

    申请号:US17941205

    申请日:2022-09-09

    Abstract: A correlated double sampling (CDS) circuit, an operating method thereof, and an image sensor including the CDS circuit are disclosed. The CDS circuit includes a first comparator configured to operate based on a first bias current, and compare, with a ramp signal, a pixel voltage that is output from a pixel, during a first period and a fourth period during which the pixel operates in a low conversion gain (LCG) mode, a second comparator configured to operate based on a second bias current, and compare, with the ramp signal, the pixel voltage output from the pixel, during a second period and a third period during which the pixel operates in a high conversion gain (HCG) mode, the second period being after the first period, the third period being after the second period, and the fourth period being after the third period.

    CDS circuit, operating method thereof, and image sensor including CDS circuit

    公开(公告)号:US11445141B2

    公开(公告)日:2022-09-13

    申请号:US17355443

    申请日:2021-06-23

    Abstract: A correlated double sampling (CDS) circuit, an operating method thereof, and an image sensor including the CDS circuit are disclosed. The CDS circuit includes a first comparator configured to operate based on a first bias current, and compare, with a ramp signal, a pixel voltage that is output from a pixel, during a first period and a fourth period during which the pixel operates in a low conversion gain (LCG) mode, a second comparator configured to operate based on a second bias current, and compare, with the ramp signal, the pixel voltage output from the pixel, during a second period and a third period during which the pixel operates in a high conversion gain (HCG) mode, the second period being after the first period, the third period being after the second period, and the fourth period being after the third period.

    Semiconductor device and retention test method

    公开(公告)号:US12237035B2

    公开(公告)日:2025-02-25

    申请号:US18113165

    申请日:2023-02-23

    Abstract: A semiconductor device includes: a memory test circuit that outputs a fourth signal based on a logic level of a second signal corresponding to a first signal output by a host and a logic level of a third signal; a memory device that becomes active or inactive based on a logic level of the fourth signal; and a test logic that outputs the third signal and performs a retention test on the memory device based on the logic level of the second signal.

    Image sensor and method of manufacturing the same

    公开(公告)号:US12224295B2

    公开(公告)日:2025-02-11

    申请号:US17455246

    申请日:2021-11-17

    Abstract: A method of manufacturing an image sensor includes forming a first dopant region having a second conductivity type in a semiconductor substrate including first and second surfaces. The semiconductor substrate has a first conductivity type different from the second conductivity type. The method further includes forming a pixel isolation structure defining pixel regions in the semiconductor substrate, forming a vertical trench by patterning the first surface in each of the pixel regions, forming a mask pattern exposing each of the pixel regions on the first surface, in which the mask pattern includes a residual mask pattern filling at least a portion of the vertical trench, forming a second dopant region having the second conductivity type in the semiconductor substrate by using the mask pattern as an ion-implantation mask, in which the second dopant region is adjacent to the vertical trench, and forming a transfer gate electrode in the vertical trench.

    CDS circuit, operating method thereof, and image sensor including CDS circuit

    公开(公告)号:US11825227B2

    公开(公告)日:2023-11-21

    申请号:US17941205

    申请日:2022-09-09

    CPC classification number: H04N25/75 H04N25/59

    Abstract: A correlated double sampling (CDS) circuit, an operating method thereof, and an image sensor including the CDS circuit are disclosed. The CDS circuit includes a first comparator configured to operate based on a first bias current, and compare, with a ramp signal, a pixel voltage that is output from a pixel, during a first period and a fourth period during which the pixel operates in a low conversion gain (LCG) mode, a second comparator configured to operate based on a second bias current, and compare, with the ramp signal, the pixel voltage output from the pixel, during a second period and a third period during which the pixel operates in a high conversion gain (HCG) mode, the second period being after the first period, the third period being after the second period, and the fourth period being after the third period.

    CDS CIRCUIT, OPERATING METHOD THEREOF, AND IMAGE SENSOR INCLUDING CDS CIRCUIT

    公开(公告)号:US20220060647A1

    公开(公告)日:2022-02-24

    申请号:US17355443

    申请日:2021-06-23

    Abstract: A correlated double sampling (CDS) circuit, an operating method thereof, and an image sensor including the CDS circuit are disclosed. The CDS circuit includes a first comparator configured to operate based on a first bias current, and compare, with a ramp signal, a pixel voltage that is output from a pixel, during a first period and a fourth period during which the pixel operates in a low conversion gain (LCG) mode, a second comparator configured to operate based on a second bias current, and compare, with the ramp signal, the pixel voltage output from the pixel, during a second period and a third period during which the pixel operates in a high conversion gain (HCG) mode, the second period being after the first period, the third period being after the second period, and the fourth period being after the third period.

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