公开(公告)号：US20190172717A1

公开(公告)日：2019-06-06

申请号：US16030212

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG-MIN KO ,  HYUK WOO KWON ,  JUN-WON LEE

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/033 ,  G03F7/20

CPC classification number: H01L21/3081 ,  G03F7/70033 ,  H01L21/02115 ,  H01L21/033 ,  H01L21/31144 ,  H01L21/32135 ,  H01L21/32139

Abstract: Methods for fabricating a semiconductor device are provided including sequentially forming a first hard mask layer, a second hard mask layer and a photoresist layer on a target layer, patterning the photoresist layer to form a photoresist pattern, sequentially patterning the second hard mask layer and the first hard mask layer using the photoresist pattern as an etching mask to form a first hard mask pattern and a second hard mask pattern on the first hard mask pattern, and etching the target layer using the first hard mask pattern and the second hard mask pattern as an etching mask, wherein the second hard mask layer includes impurity-doped amorphous silicon.

公开(公告)号：US20200066800A1

公开(公告)日：2020-02-27

申请号：US16396650

申请日：2019-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYONGJU KIM ,  YOUNG-MIN KO ,  JONGUK KIM ,  KWANGMIN PARK ,  JEONGHEE PARK ,  DONGSUNG CHOI

IPC: H01L27/24 ,  H01L45/00

Abstract: A variable resistanvce memory device may include a plurality of first conductive lines extending in a first direction, a plurality of second conductive lines extending in a second direction, a plurality of memory cells, each memory cell at a respective intersection, with respect to a top down view, between a corresponding one of the first conductive lines and a corresponding one of the second conductive lines, each memory cell comprising a variable resistance structure and a switching element sandwiched between a top electrode and a bottom electrode, and a first dielectric layer filling a space between the switching elements of the memory cells. A top surface of the first dielectric layer is disposed between bottom and top surfaces of the top electrodes of the memory cells.