公开(公告)号：US10153277B2

公开(公告)日：2018-12-11

申请号：US15390361

申请日：2016-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-suk Tak ,  Tae-jong Lee ,  Gi-gwan Park ,  Ji-myoung Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L27/02 ,  H01L29/08 ,  H01L29/423 ,  H01L21/8258

Abstract: An integrated circuit device includes: a pair of width-setting patterns over a substrate, the pair of width-setting patterns defining a width of a gate structure space in a first direction and extending in a second direction intersecting with the first direction. A gate electrode layer is provided that extends in the gate structure space along the second direction. A gate insulating layer is provided in the gate structure space and between the substrate and the gate electrode layer. An insulating spacer is provides on the pair of width-setting patterns, the insulating spacer covering both sidewalls of the gate electrode layer, wherein the pair of width-setting patterns have a carbon content that is greater than a carbon content of the insulating spacer.

公开(公告)号：US10460927B2

公开(公告)日：2019-10-29

申请号：US15296220

申请日：2016-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-suk Tak ,  Tae-jong Lee ,  Bon-young Koo ,  Ki-yeon Park ,  Sung-hyun Choi

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092 ,  H01L27/11 ,  C23C16/455 ,  C23C16/30 ,  H01L29/78

Abstract: A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.

公开(公告)号：US09859393B2

公开(公告)日：2018-01-02

申请号：US15401659

申请日：2017-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-suk Tak ,  Tae-jong Lee ,  Hyun-seung Kim ,  Bon-young Koo ,  Ki-yeon Park ,  Gi-gwan Park ,  Mi-seon Park

IPC: H01L29/76 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/4983 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

Abstract: A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.

公开(公告)号：US10096688B2

公开(公告)日：2018-10-09

申请号：US15206868

申请日：2016-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-suk Tak ,  Gi-gwan Park ,  Tae-jong Lee ,  Bon-young Koo ,  Ki-yeon Park ,  Sung-hyun Choi

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

Abstract: An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area; a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area; a gate dielectric layer disposed between the nanosheet and the gate; a source and drain region formed on the fin type active area and connected to one end of the nanosheet; a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer structure.

公开(公告)号：US20170110554A1

公开(公告)日：2017-04-20

申请号：US15206868

申请日：2016-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-suk Tak ,  Gi-gwan Park ,  Tae-jong Lee ,  Bon-young Koo ,  Ki-yeon Park ,  Sung-hyun Choi

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/4991 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/78696

Abstract: An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area; a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area; a gate dielectric layer disposed between the nanosheet and the gate; a source and drain region formed on the fin type active area and connected to one end of the nanosheet; a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer structure.

公开(公告)号：US10529555B2

公开(公告)日：2020-01-07

申请号：US16422375

申请日：2019-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-suk Tak ,  Tae-jong Lee ,  Bon-young Koo ,  Ki-yeon Park ,  Sung-hyun Choi

IPC: H01L21/02 ,  C23C16/30 ,  H01L29/66 ,  H01L29/49 ,  H01L27/11 ,  H01L27/092 ,  C23C16/455 ,  H01L29/78

Abstract: A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.

公开(公告)号：US20170222014A1

公开(公告)日：2017-08-03

申请号：US15401659

申请日：2017-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-suk Tak ,  Tae-jong Lee ,  Hyun-seung Kim ,  Bon-young Koo ,  Ki-yeon Park ,  Gi-gwan Park ,  Mi-seon Park

IPC: H01L29/49 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L29/4983 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

Abstract: A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.