公开(公告)号：US20240087856A1

公开(公告)日：2024-03-14

申请号：US18447479

申请日：2023-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Son ,  Sunggil Kang ,  Kangmin Do ,  Youngsun Kim ,  Younghoo Kim ,  Sangjin An

IPC: H01J37/32 ,  C23C16/455

CPC classification number: H01J37/32715 ,  C23C16/45565 ,  H01J37/32082 ,  H01J37/32477 ,  H01J37/32633 ,  H01J2237/3321 ,  H01J2237/334

Abstract: A substrate treating apparatus includes a process chamber configured to perform plasma treatment, a substrate support in a lower portion of the process chamber and configured to support a substrate, a showerhead in an upper portion of the process chamber and configured to supply a process gas for the plasma treatment toward the substrate, and a baffle surrounding the substrate support. The substrate support functions as a first electrode for generating plasma, the showerhead and the baffle function as a second electrode for generating the plasma, the baffle has a variable height, and an area of the second electrode varies as a height of the baffle varies.

公开(公告)号：US20190122867A1

公开(公告)日：2019-04-25

申请号：US15991500

申请日：2018-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Ki Nam ,  Sunggil Kang ,  Sungyong Lim ,  Beomjin Yoo ,  Akira Koshiishi ,  Vasily Pashkovskiy ,  Kwangyoub Heo

IPC: H01J37/32 ,  H01J1/02

Abstract: A hollow cathode includes an insulation plate having cathode holes. Bottom electrodes are below the insulation plate. The bottom electrodes define first holes having a width greater than a width of the cathode holes. Top electrodes are at an opposite side of the insulation plate from the bottom electrodes. The top electrodes define second holes aligned with the first holes along a direction orthogonal to the upper surface of the insulation plate.

公开(公告)号：US20240203701A1

公开(公告)日：2024-06-20

申请号：US18523234

申请日：2023-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonku Kwon ,  Sunggil Kang ,  Chanyeong Jeong ,  Jeongmin Bang ,  Yeongkwang Lee ,  Ilgon Choi

IPC: H01J37/32

CPC classification number: H01J37/32522 ,  H01J37/32422 ,  H01J2237/002

Abstract: A substrate processing apparatus includes a chamber including a first space and a second space, a substrate support in the first space and configured to support a substrate, a plasma source configured to generate plasma in the second space, an ion blocker between the second space and the first space, the ion blocker including through-holes configured to pass therethrough radicals of the plasma from the second space to the first space and provide the radicals to the substrate, and a temperature controller including a plurality of heaters connected to the ion blocker, one or more chillers, and a controller configured to control output of the plurality of heaters and output of the one or more chillers, where the ion blocker includes a plurality of regions, each of the plurality of regions including a heating line, one or more boundary regions.

公开(公告)号：US11289308B2

公开(公告)日：2022-03-29

申请号：US16860745

申请日：2020-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjin An ,  Minseop Park ,  Chanyeong Jeong ,  Sunggil Kang ,  Yeongkwang Lee

IPC: H01J37/32 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/683

Abstract: A substrate processing apparatus includes a process chamber including a plasma generation region configured to receive at least one first process gas and have first radio-frequency (RF) power applied thereto, to generate plasma; a gas distribution region configured to supply the at least one first process gas to the plasma generation region; a gas mixing region configured to receive at least one second process gas and radicals generated in the plasma generation region to generate an etchant based on the radicals being mixed with the at least one second process gas; a pedestal on which a substrate is disposed; a processing region in which the pedestal is installed; and a shower head configured to supply the etchant from the gas mixing region to the processing region, the substrate disposed on the pedestal being processed by the etchant. The gas mixing region is separate from each of the plasma generation region and the processing region.

公开(公告)号：US11798788B2

公开(公告)日：2023-10-24

申请号：US17091433

申请日：2020-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Ki Nam ,  Sunggil Kang ,  Sungyong Lim ,  Beomjin Yoo ,  Akira Koshiishi ,  Vasily Pashkovskiy ,  Kwangyoub Heo

IPC: H01L21/3065 ,  H01J37/32 ,  H01J1/02

CPC classification number: H01J37/32596 ,  H01J1/025 ,  H01J37/32009 ,  H01J37/32899

Abstract: A hollow cathode includes an insulation plate having cathode holes. Bottom electrodes are below the insulation plate. The bottom electrodes define first holes having a width greater than a width of the cathode holes. Top electrodes are at an opposite side of the insulation plate from the bottom electrodes. The top electrodes define second holes aligned with the first holes along a direction orthogonal to the upper surface of the insulation plate.

公开(公告)号：US10950414B2

公开(公告)日：2021-03-16

申请号：US15983178

申请日：2018-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Ki Nam ,  Akira Koshiishi ,  Kwangyoub Heo ,  Sunggil Kang ,  Beomjin Yoo ,  Sungyong Lim ,  Vasily Pashkovskiy

IPC: H01L21/00 ,  C23C16/00 ,  H01J37/32 ,  H01L21/66 ,  H01L21/3065 ,  H01L21/683

Abstract: Disclosed are a plasma processing apparatus and a method of manufacturing a semiconductor device using the same. The plasma processing apparatus comprises a chamber, an electrostatic chuck in the chamber and loading a substrate, a plasma electrode generating an upper plasma on the electrostatic chuck; and a hollow cathode between the plasma electrode and the electrostatic chuck, wherein the hollow cathode generates a lower plasma below the upper plasma. The hollow cathode comprises cathode holes each having a size less than a thickness of a plasma sheath of the upper plasma.

公开(公告)号：US20240282586A1

公开(公告)日：2024-08-22

申请号：US18640481

申请日：2024-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanyeong Jeong ,  Hoseop Choi ,  Sunggil Kang ,  Dongkyu Shin ,  Sangjin An

IPC: H01L21/324 ,  H01J37/32 ,  H01L21/311 ,  H01L21/67

CPC classification number: H01L21/324 ,  H01J37/321 ,  H01J37/32229 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32724 ,  H01L21/31116 ,  H01L21/67069 ,  H01L21/67109

Abstract: A wafer processing method includes supplying a first process gas into a wafer processing apparatus, lowering a temperature of the wafer, generating plasma using the first process gas, supplying a second process gas and mixing the second process gas with the plasma, performing a plasma process on the wafer using the plasma and the second process gas, and performing an annealing process on the wafer on which the plasma process has been performed. The lowering of the temperature of the wafer includes increasing an internal pressure of the wafer processing apparatus.

公开(公告)号：US11990348B2

公开(公告)日：2024-05-21

申请号：US17184279

申请日：2021-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanyeong Jeong ,  Hoseop Choi ,  Sunggil Kang ,  Dongkyu Shin ,  Sangjin An

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/311 ,  H01L21/324 ,  H01L21/67

CPC classification number: H01L21/324 ,  H01J37/321 ,  H01J37/32229 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32724 ,  H01L21/31116 ,  H01L21/67069 ,  H01L21/67109

Abstract: A wafer processing method includes supplying a first process gas into a wafer processing apparatus, lowering a temperature of the wafer, generating plasma using the first process gas, supplying a second process gas and mixing the second process gas with the plasma, performing a plasma process on the wafer using the plasma and the second process gas, and performing an annealing process on the wafer on which the plasma process has been performed. The lowering of the temperature of the wafer includes increasing an internal pressure of the wafer processing apparatus.

公开(公告)号：US10522332B2

公开(公告)日：2019-12-31

申请号：US16421433

申请日：2019-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwang Lee ,  Sunggil Kang ,  Sang Ki Nam ,  Kwangyoub Heo ,  Kyuhee Han

IPC: H01J37/317 ,  H01J37/32 ,  H01L21/683

Abstract: A chamber has an upper housing and a lower housing and receives a reaction gas. A first plasma source includes electron beam sources providing electron beams into the upper housing to generate an upper plasma. A second plasma source includes holes generating a lower plasma within the holes connecting the upper housing and the lower housing. Radicals of the upper plasma, radicals of the lower plasma, and ions of the lower plasma are provided, through the holes, to the lower housing so that the lower housing has radicals and ions at a predetermined ratio of the ions to the radicals in concentration. The second plasma source divides the chamber into the upper housing and the lower housing. A wafer chuck is positioned in the lower housing to receive a wafer.

公开(公告)号：US10347468B2

公开(公告)日：2019-07-09

申请号：US15870800

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwang Lee ,  Sunggil Kang ,  Sang Ki Nam ,  Kwangyoub Heo ,  Kyuhee Han

IPC: H01J37/32 ,  H01L21/683

Abstract: A chamber has an upper housing and a lower housing and receives a reaction gas. A first plasma source includes electron beam sources providing electron beams into the upper housing to generate an upper plasma. A second plasma source includes holes generating a lower plasma within the holes connecting the upper housing and the lower housing. Radicals of the upper plasma, radicals of the lower plasma, and ions of the lower plasma are provided, through the holes, to the lower housing so that the lower housing has radicals and ions at a predetermined ratio of the ions to the radicals in concentration. The second plasma source divides the chamber into the upper housing and the lower housing. A wafer chuck is positioned in the lower housing to receive a wafer.