公开(公告)号：US10665558B2

公开(公告)日：2020-05-26

申请号：US16036198

申请日：2018-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sihong Kim ,  Young-Hoon Son ,  Taeyoung Oh ,  Kyung-Soo Ha

IPC: H01L23/00 ,  G11C5/06 ,  G11C8/10 ,  G11C5/04 ,  G11C5/02

Abstract: A semiconductor memory includes a plurality of first pads arranged in a first direction, a plurality of second pads arranged parallel to the plurality of first pads and in the first direction, a plurality of third pads arranged in a second direction perpendicular to the first direction, and a plurality of fourth pads arranged in the second direction. The semiconductor memory further includes first interconnection wires extending from the plurality of first pads in the second direction, the first interconnection wires being connected to the plurality of third pads, and second interconnection wires extending from the plurality of second pads in an opposite direction to the second direction, the second interconnection wires being connected to the plurality of fourth pads.

公开(公告)号：US20190130950A1

公开(公告)日：2019-05-02

申请号：US15985200

申请日：2018-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun Kim ,  Sihong Kim

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4091

CPC classification number: G11C11/4093 ,  G11C5/025 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4091 ,  G11C29/028 ,  G11C2207/105 ,  G11C2207/107 ,  G11C2207/2254

Abstract: A semiconductor memory device includes a memory core that performs reading and writing of data, data delivery and training blocks that are connected between first pads and the memory core, and at least one data delivery, clock generation and training block that is connected between at least one second pad and the memory core. In a first training operation, the data delivery and training blocks output first training data, received through the first pads, through the first pads as second training data. In a second training operation, at least one of the data delivery and training blocks outputs third training data, received through the at least one second pad, through at least one of the first pads as fourth training data. The second training data and the fourth training data are output in synchronization with read data strobe signals output through the at least one second pad.

公开(公告)号：US10777246B2

公开(公告)日：2020-09-15

申请号：US16778431

申请日：2020-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Yeon Doo ,  Seungjun Bae ,  Sihong Kim ,  Hosung Song

IPC: G11C8/00 ,  G11C8/18 ,  G06F11/10 ,  G11C7/22 ,  G11C5/04 ,  G11C11/4076 ,  G11C29/04

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

公开(公告)号：US10347323B2

公开(公告)日：2019-07-09

申请号：US15985200

申请日：2018-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun Kim ,  Sihong Kim

IPC: G11C11/40 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4091 ,  G11C7/22

Abstract: A semiconductor memory device includes a memory core that performs reading and writing of data, data delivery and training blocks that are connected between first pads and the memory core, and at least one data delivery, clock generation and training block that is connected between at least one second pad and the memory core. In a first training operation, the data delivery and training blocks output first training data, received through the first pads, through the first pads as second training data. In a second training operation, at least one of the data delivery and training blocks outputs third training data, received through the at least one second pad, through at least one of the first pads as fourth training data. The second training data and the fourth training data are output in synchronization with read data strobe signals output through the at least one second pad.

公开(公告)号：US10236045B2

公开(公告)日：2019-03-19

申请号：US13828869

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Yeon Doo ,  Seungjun Bae ,  Sihong Kim ,  Hosung Song

IPC: G11C7/00 ,  G11C8/18 ,  G11C5/04 ,  G11C7/22 ,  G11C11/4076 ,  G06F11/10 ,  G11C8/00 ,  G11C29/04

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

公开(公告)号：USRE49467E1

公开(公告)日：2023-03-21

申请号：US17131149

申请日：2020-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun Kim ,  Sihong Kim

IPC: G11C11/40 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4091 ,  G11C7/22 ,  G11C5/02 ,  G11C29/02 ,  G11C11/4076

Abstract: A semiconductor memory device includes a memory core that performs reading and writing of data, data delivery and training blocks that are connected between first pads and the memory core, and at least one data delivery, clock generation and training block that is connected between at least one second pad and the memory core. In a first training operation, the data delivery and training blocks output first training data, received through the first pads, through the first pads as second training data. In a second training operation, at least one of the data delivery and training blocks outputs third training data, received through the at least one second pad, through at least one of the first pads as fourth training data. The second training data and the fourth training data are output in synchronization with read data strobe signals output through the at least one second pad.

公开(公告)号：US20200168259A1

公开(公告)日：2020-05-28

申请号：US16778431

申请日：2020-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Yeon Doo ,  Seungjun Bae ,  Sihong Kim ,  Hosung Song

IPC: G11C8/18 ,  G06F11/10 ,  G11C11/4076 ,  G11C7/22 ,  G11C5/04

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

公开(公告)号：US10593387B2

公开(公告)日：2020-03-17

申请号：US16274860

申请日：2019-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Yeon Doo ,  Seungjun Bae ,  Sihong Kim ,  Hosung Song

IPC: G11C8/00 ,  G11C8/18 ,  G11C5/04 ,  G11C7/22 ,  G11C11/4076 ,  G06F11/10 ,  G11C29/04

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.