公开(公告)号：US10777246B2

公开(公告)日：2020-09-15

申请号：US16778431

申请日：2020-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Yeon Doo ,  Seungjun Bae ,  Sihong Kim ,  Hosung Song

IPC: G11C8/00 ,  G11C8/18 ,  G06F11/10 ,  G11C7/22 ,  G11C5/04 ,  G11C11/4076 ,  G11C29/04

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

公开(公告)号：US10236045B2

公开(公告)日：2019-03-19

申请号：US13828869

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Yeon Doo ,  Seungjun Bae ,  Sihong Kim ,  Hosung Song

IPC: G11C7/00 ,  G11C8/18 ,  G11C5/04 ,  G11C7/22 ,  G11C11/4076 ,  G06F11/10 ,  G11C8/00 ,  G11C29/04

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

公开(公告)号：US20200168259A1

公开(公告)日：2020-05-28

申请号：US16778431

申请日：2020-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Yeon Doo ,  Seungjun Bae ,  Sihong Kim ,  Hosung Song

IPC: G11C8/18 ,  G06F11/10 ,  G11C11/4076 ,  G11C7/22 ,  G11C5/04

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

公开(公告)号：US10593387B2

公开(公告)日：2020-03-17

申请号：US16274860

申请日：2019-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Yeon Doo ,  Seungjun Bae ,  Sihong Kim ,  Hosung Song

IPC: G11C8/00 ,  G11C8/18 ,  G11C5/04 ,  G11C7/22 ,  G11C11/4076 ,  G06F11/10 ,  G11C29/04

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

公开(公告)号：US10032523B2

公开(公告)日：2018-07-24

申请号：US15450588

申请日：2017-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongpil Son ,  Hosung Song ,  Wonchang Jung

IPC: G11C29/02 ,  G11C7/10 ,  G11C7/22 ,  H01L25/065

Abstract: A memory device includes a memory cell array, a multiplexing circuit, and a control logic circuit. The memory cell array includes a first sub memory cell array, a second sub memory cell array, and a third sub memory cell array. The multiplexing circuit selects the first sub memory cell array, the second sub memory cell array, and the third sub memory cell array in a first mode of operation, and when the first sub memory cell array is defective in a second mode of operation, the multiplexing circuit selects the second sub memory cell array and the third sub memory cell array. The control logic circuit selects the first mode of operation or the second mode of operation. The control logic circuit controls the multiplexing circuit so that the first, second and third sub memory cell arrays are connected to input or output pads.