公开(公告)号：US20240177749A1

公开(公告)日：2024-05-30

申请号：US18354869

申请日：2023-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseok Yang ,  Eungchang Lee ,  Seula Ryu ,  Minhwan An ,  Yunkyeong Jeong ,  Chul-Hwan Choo

IPC: G11C7/10 ,  G11C5/06

CPC classification number: G11C7/1084 ,  G11C5/06 ,  G11C7/1057

Abstract: A memory device includes a base die that includes a data signal bump configured to receive a data signal, a first memory stack that includes first memory dies sequentially stacked on the base die, and a second memory stack that includes second memory dies sequentially stacked on the base die and spaced from the first memory stack in a direction parallel to an upper surface of the base die. The base die is configured to selectively provide the data signal received through the data signal bump to one of the first memory stack or the second memory stack based on a selection signal.

公开(公告)号：US20240196633A1

公开(公告)日：2024-06-13

申请号：US18529365

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseok Yang ,  Seula Ryu ,  Jaewoo Shin ,  Minhwan An ,  Seongjin Lee ,  Sunghak Lee ,  Eungchang Lee ,  Yunkyeong Jeong ,  Jinsuk Chung

IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: A memory device and a system includes a plurality of physical interfaces. The memory device includes a buffer die including a first interface circuit and a second interface circuit configured to communicate with an external device and a memory die stack mounted on the buffer die and including a plurality of stacked memory dies. The plurality of memory dies are electrically connected to the first interface circuit and the second interface circuit, the first interface circuit is configured to activate responsive to a first selection signal, and the second interface circuit is configured to activate responsive to a second selection signal. The first selection signal and the second selection signal are received from a memory controller external to the memory device.

公开(公告)号：US20240188309A1

公开(公告)日：2024-06-06

申请号：US18452616

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseok Yang ,  Yunkyeong Jeong ,  Seula Ryu ,  Dong Gi Lee ,  Minhwan An ,  Eungchang Lee ,  Chul-Hwan Choo

IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: Disclosed is a memory device which includes a base die that includes a pair of second dies and a first die that is between the pair of second dies, and a memory stack that includes memory dies sequentially stacked on the base die in a vertical direction. The first die is electrically connected to the memory stack, and the first die includes a logic transistor including a channel of a three-dimensional structure.