公开(公告)号：US10891204B2

公开(公告)日：2021-01-12

申请号：US16200948

申请日：2018-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Hyung Kim ,  Chul-Hwan Choo

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/07 ,  G06F12/00

Abstract: A memory system including: a memory apparatus including a buffer die, core dies disposed on the buffer die, channels and a through silicon via configured to transmit a signal between the buffer die and at least one of the core dies; a memory controller configured to output a command signal and an address signal to the memory apparatus, to output a data signal to the memory apparatus and to receive the data signal from the memory apparatus; and an interposer including channel paths for connecting the memory controller and the channels, wherein the memory apparatus further includes a path selector for changing a connection state between the channels and channel paths, and when an error is detected in a first connection state between the channels and the channel paths, the path selector changes the first connection state to a second connection state.

公开(公告)号：US20240188309A1

公开(公告)日：2024-06-06

申请号：US18452616

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseok Yang ,  Yunkyeong Jeong ,  Seula Ryu ,  Dong Gi Lee ,  Minhwan An ,  Eungchang Lee ,  Chul-Hwan Choo

IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: Disclosed is a memory device which includes a base die that includes a pair of second dies and a first die that is between the pair of second dies, and a memory stack that includes memory dies sequentially stacked on the base die in a vertical direction. The first die is electrically connected to the memory stack, and the first die includes a logic transistor including a channel of a three-dimensional structure.

公开(公告)号：US20240177749A1

公开(公告)日：2024-05-30

申请号：US18354869

申请日：2023-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseok Yang ,  Eungchang Lee ,  Seula Ryu ,  Minhwan An ,  Yunkyeong Jeong ,  Chul-Hwan Choo

IPC: G11C7/10 ,  G11C5/06

CPC classification number: G11C7/1084 ,  G11C5/06 ,  G11C7/1057

Abstract: A memory device includes a base die that includes a data signal bump configured to receive a data signal, a first memory stack that includes first memory dies sequentially stacked on the base die, and a second memory stack that includes second memory dies sequentially stacked on the base die and spaced from the first memory stack in a direction parallel to an upper surface of the base die. The base die is configured to selectively provide the data signal received through the data signal bump to one of the first memory stack or the second memory stack based on a selection signal.

公开(公告)号：US11928363B2

公开(公告)日：2024-03-12

申请号：US17713599

申请日：2022-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Ha Hwang ,  Chul-Hwan Choo ,  Gye Sik Oh ,  Young Bin Lee ,  Sung Won Jo

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method of operating a host device to control a storage device which includes a register is provided. The method includes: providing the storage device with a partial array refresh setting indicating a non-masking segment among a masking segment and the non-masking segment; providing a refresh command to the storage device; and providing a write command for the masking segment to the storage device to control the storage device to store data while a partial array refresh is performed in the storage device based on the refresh command.

公开(公告)号：US10727200B2

公开(公告)日：2020-07-28

申请号：US16115741

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Hwan Choo ,  Woong-Jae Song

IPC: G06F13/36 ,  H01L25/065 ,  H01L25/18 ,  G11C8/18 ,  G11C5/06 ,  G06F3/06 ,  G11C5/04

Abstract: A memory device includes a buffer die including a first bump array and a second bump array spaced apart from each other in a first direction parallel to a lower surface of the buffer die; a first memory die stacked on the buffer die through a plurality of first through silicon vias and including banks; and a second memory die stacked on the first memory die by a plurality of second through silicon vias and including banks, wherein the first bump array is provided for a first channel to communicate between the first and second memory dies and a first processor, wherein the second bump array is provided for a second channel to communicate between the first and second memory dies and a second processor, and wherein the first channel and the second channel are independent of each other such that banks allocated to the first channel are accessed only by the first processor not the second processor through the first channel and banks allocated to the second channel are accessed only by the second processor not the first processor through the second channel.