公开(公告)号：US20230247836A1

公开(公告)日：2023-08-03

申请号：US18154982

申请日：2023-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin KANG ,  Bio KIM ,  Hyung Joon KIM ,  Kyungwook PARK

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: Disclosed are 3D semiconductor memory devices and electronic systems including the same. The 3D semiconductor memory device comprises a stack structure including interlayer dielectric layers and gate electrodes that are alternately and repeatedly stacked on a substrate, vertical channel structures in vertical channel holes that penetrate the stack structure and each including a charge storage layer, a tunneling dielectric layer, and a vertical semiconductor pattern that are sequentially cover an inner sidewall of each of the vertical channel holes, and a diffusion stop layer between the gate electrodes and the charge storage layer. The diffusion stop layer includes a dielectric material having a dielectric constant of greater than about 0 and less than about 5.

公开(公告)号：US20210313341A1

公开(公告)日：2021-10-07

申请号：US17029269

申请日：2020-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin KANG ,  Hanvit YANG

IPC: H01L27/11575 ,  H01L27/11582 ,  H01L23/48 ,  H01L23/528

Abstract: A semiconductor device includes a substrate, a lower structure on the substrate, the lower structure including a first wiring structure, a second wiring structure, and a lower insulating structure covering the first and second wiring structures, a first pattern layer including a plate portion and a via portion, the plate portion being on the lower insulating structure and the via portion extending into the lower insulating structure from a lower portion of the plate portion and overlapping the first wiring structure, a graphene-like carbon material layer in contact with the via portion and the first wiring structure between the via portion and the first wiring structure, gate layers stacked in a vertical direction perpendicular to an upper surface of the substrate and spaced apart from each other on the first pattern layer, and a memory vertical structure penetrating through the gate layers in the vertical direction.

公开(公告)号：US20250072087A1

公开(公告)日：2025-02-27

申请号：US18583269

申请日：2024-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwook PARK ,  Sangmin KANG ,  Changwoo SEO ,  Suyoun SONG ,  Dain LEE

IPC: H01L29/417 ,  H01L23/528

Abstract: A semiconductor device may include first and second active patterns, each including a center portion and an edge portion, the center portion of the first active pattern and the edge portion of the second active pattern adjacent to each other, a device isolation pattern between the first and second active patterns, a bit line node contact on the center portion of the first active pattern, a bit line on the bit line node contact, a storage node contact on the edge portion of the second active pattern, a bit line spacer between the bit line and the storage node contact, and a gapfill insulating pattern between a lower portion of the bit line spacer and the storage node contact. The center portion of the first active pattern may include a center oxide region in an upper portion thereof.

公开(公告)号：US20220416052A1

公开(公告)日：2022-12-29

申请号：US17696258

申请日：2022-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin KANG ,  Junghwan KIM

IPC: H01L29/45 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/10

Abstract: A semiconductor device includes a substrate; gate electrodes spaced apart from each other and stacked in a direction, perpendicular to an upper surface of the substrate; first and second horizontal conductive layers sequentially stacked between the substrate and the gate electrodes; and a channel structure passing through the gate electrodes and extending perpendicularly, and including a channel layer contacting the first horizontal conductive layer, wherein the channel layer has a region having a reduced diameter below a first level in which a lower surface of a lowermost gate electrode is located, among the gate electrodes, and the channel structure further includes a metal silicide region located below the first level and in the channel structure to contact the channel layer.

公开(公告)号：US20220344368A1

公开(公告)日：2022-10-27

申请号：US17668889

申请日：2022-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmin KANG ,  Sunggil KIM ,  Jeeseung LIM

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: Disclosed are semiconductor devices and electronic systems including the same. The semiconductor device includes a stack structure including electrodes vertically stacked on a semiconductor layer, a source semiconductor pattern between the semiconductor layer and the stack structure, a support semiconductor pattern between the stack structure and the source semiconductor pattern, and a vertical structure penetrating the stack structure, the support semiconductor pattern, and the source semiconductor pattern. The vertical structure includes a vertical channel pattern in which a part of a sidewall is in contact with the source semiconductor pattern. The vertical channel pattern includes an upper portion adjacent to the stack structure, a lower portion adjacent to the source semiconductor pattern, and a middle portion adjacent to the support semiconductor pattern. The upper portion has a first diameter. The lower portion has a second diameter. The middle portion has a third diameter less than the first and second diameters.