公开(公告)号：US10304734B2

公开(公告)日：2019-05-28

申请号：US16046081

申请日：2018-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Kyung You ,  Jong Min Baek ,  Sang Shin Jang ,  Byung Hee Kim ,  Vietha Nguyen ,  Nae In Lee ,  Woo Jin Lee ,  Eun Ji Jung ,  Kyu Hee Han

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.

公开(公告)号：US10770447B2

公开(公告)日：2020-09-08

申请号：US16400465

申请日：2019-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Jin Lee ,  Seok Ho Kim ,  Kwang Jin Moon ,  Byung Lyul Park ,  Nae In Lee

IPC: H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/67

Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.

公开(公告)号：US10325897B2

公开(公告)日：2019-06-18

申请号：US15705427

申请日：2017-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Jin Lee ,  Seok Ho Kim ,  Kwang Jin Moon ,  Byung Lyul Park ,  Nae In Lee

IPC: H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67

Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.

公开(公告)号：US10128148B2

公开(公告)日：2018-11-13

申请号：US15636889

申请日：2017-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Viet Ha Nguyen ,  Nae In Lee ,  Thomas Oszinda ,  Byung Hee Kim ,  Jong Min Baek ,  Tae Jin Yim

IPC: H01L21/768

Abstract: Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.

公开(公告)号：US20180138164A1

公开(公告)日：2018-05-17

申请号：US15705427

申请日：2017-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Jin LEE ,  Seok Ho Kim ,  Kwang Jin Moon ,  Byung Lyul Park ,  Nae In Lee

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/3065 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/67 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00

Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.

公开(公告)号：US10062609B2

公开(公告)日：2018-08-28

申请号：US15393506

申请日：2016-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Kyung You ,  Jong Min Baek ,  Sang Shin Jang ,  Byung Hee Kim ,  Vietha Nguyen ,  Nae In Lee ,  Woo Jin Lee ,  Eun Ji Jung ,  Kyu Hee Han

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76883 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295 ,  H01L2221/1021

Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.