公开(公告)号：US11705376B2

公开(公告)日：2023-07-18

申请号：US17520854

申请日：2021-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-soon Park ,  Hyun-Soo Chung ,  Chan-Ho Lee

IPC: H01L23/48 ,  H01L21/66 ,  G11C29/12

CPC classification number: H01L22/32 ,  G11C29/1201 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

公开(公告)号：US11189535B2

公开(公告)日：2021-11-30

申请号：US16868209

申请日：2020-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-soon Park ,  Hyun-Soo Chung ,  Chan-Ho Lee

IPC: H01L23/48 ,  H01L21/66 ,  G11C29/12

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

公开(公告)号：US20200266114A1

公开(公告)日：2020-08-20

申请号：US16868209

申请日：2020-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-soon Park ,  Hyun-Soo Chung ,  Chan-Ho Lee

IPC: H01L21/66 ,  G11C29/12

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

公开(公告)号：US10008462B2

公开(公告)日：2018-06-26

申请号：US15226231

申请日：2016-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Tae-je Cho ,  Yong-hwan Kwon ,  Hyung-gil Baek ,  Hyun-soo Chung ,  Seung-kwan Ryu ,  Myeong-soon Park

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L24/08 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/08058 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/19105 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/034 ,  H01L2224/1146 ,  H01L2224/0361 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01024 ,  H01L2924/01022

Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.

公开(公告)号：US20170084558A1

公开(公告)日：2017-03-23

申请号：US15226231

申请日：2016-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Tae-je Cho ,  Yong-hwan Kwon ,  Hyung-gil Baek ,  Hyun-soo Chung ,  Seung-kwan Ryu ,  Myeong-soon Park

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L24/08 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/08058 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/19105 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/034 ,  H01L2224/1146 ,  H01L2224/0361 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01024 ,  H01L2924/01022

Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.