公开(公告)号：US11050683B2

公开(公告)日：2021-06-29

申请号：US15953179

申请日：2018-04-13

Applicant: Samsung Electronics Co., Ltd

Inventor： Hyong Jin Ban ,  Yong Suk Kwon ,  Tae Sun Yeoum ,  Myeong Cheol Kim ,  Sung Jin Kim ,  Yoon Sung Nam ,  Pei Huang ,  Qia Wang ,  Zhinan Zhou

IPC: H04L12/58 ,  H04L29/06 ,  H04W88/06 ,  H04L29/08 ,  G06F40/40

Abstract: An electronic device is provided. The electronic device includes a housing, a display configured to be exposed through one surface of the housing, a communication module configured to communicate over a first network compliant with a first protocol or a second network compliant with a second protocol, a processor configured to be electrically connected with the display and the communication module, and a memory configured to be electrically connected with the processor and store a specified application. The memory stores instructions, that when executed, cause the processor 420 to execute the specified application, designate a CP server by interacting with a platform server over the second network, receive an initial response message generated by the designated CP server over the first network, and verify a first identifier of the designated CP server based on the first protocol from a source of the initial response message.

公开(公告)号：US09741854B2

公开(公告)日：2017-08-22

申请号：US14959457

申请日：2015-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hee Bai ,  Kyoung Hwan Yeo ,  Seung Seok Ha ,  Seung Ju Park ,  Do Hyoung Kim ,  Myeong Cheol Kim ,  Jae Hyoung Koo ,  Ki Byung Park

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7851

Abstract: There is provided a method for manufacturing a semiconductor device including a substrate including a plurality of active regions, a plurality of gate electrodes extending in a first direction to intersect a portion of the plurality of active regions, and including first and second gate electrodes disposed to be adjacent to each other in the first direction, a gate isolation portion disposed between the first and second gate electrodes. The gate isolation portion includes a first layer and second layers disposed on both ends of the first layer in a second direction perpendicular to the first direction.