公开(公告)号：US20170358553A1

公开(公告)日：2017-12-14

申请号：US15413824

申请日：2017-01-24

Applicant: Samsung Electronics Co. Ltd.

Inventor： TAE-YEONG KIM ,  Pil-kyu KANG ,  Seok-ho KIM ,  Kwang-jin MOON ,  Ho-jin LEE

IPC: H01L23/00

CPC classification number: H01L24/94 ,  H01L24/02 ,  H01L24/05 ,  H01L24/29 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02215 ,  H01L2224/04105 ,  H01L2224/05147 ,  H01L2224/29187 ,  H01L2224/29188 ,  H01L2224/8012 ,  H01L2224/8312 ,  H01L2224/83896 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/0537 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/0549 ,  H01L2924/365 ,  H01L2224/80

Abstract: A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad, a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad, and a third barrier layer between portions of the first and second wafers where the first and second conductive pads are not bonded to each other.

公开(公告)号：US20200027784A1

公开(公告)日：2020-01-23

申请号：US16242122

申请日：2019-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-jeong PARK ,  Dong-chan LIM ,  Kwang-jin MOON ,  Ju-bin SEO ,  Ju-ll CHOI ,  Atsushi FUJISAKI

IPC: H01L21/768

Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.