公开(公告)号：US20170207158A1

公开(公告)日：2017-07-20

申请号：US15408977

申请日：2017-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil-kyu KANG ,  Ho-jin LEE ,  Byung-lyul PARK ,  Tae-yeong KIM ,  Seok-ho KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2224/16146 ,  H01L2225/06548

Abstract: A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on the first insulating layer, an intermediate device having an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer, an upper device having an upper substrate, a third insulating layer on the upper substrate, a second TSV bump on the third insulating layer, and a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad. An insulating first TSV spacer between the intermediate substrate and the TSV structure and an insulating second TSV spacer between the upper substrate and the TSV structure are spaced apart along a stacking direction.

公开(公告)号：US20140106649A1

公开(公告)日：2014-04-17

申请号：US14056270

申请日：2013-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-yeong KIM ,  Pil-kyu KANG ,  Byung-Iyul PARK ,  Jin-ho PARK

IPC: H01L21/02

CPC classification number: H01L21/02016 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381

Abstract: Wafer processing methods are provided. The methods may include cutting respective edges of a wafer and an adhesive a predetermined angle before grinding a back surface of the wafer.

Abstract translation: 提供晶片加工方法。 所述方法可以包括在研磨晶片的背面之前切割晶片和粘合剂的相应边缘预定的角度。

公开(公告)号：US20170358553A1

公开(公告)日：2017-12-14

申请号：US15413824

申请日：2017-01-24

Applicant: Samsung Electronics Co. Ltd.

Inventor： TAE-YEONG KIM ,  Pil-kyu KANG ,  Seok-ho KIM ,  Kwang-jin MOON ,  Ho-jin LEE

IPC: H01L23/00

CPC classification number: H01L24/94 ,  H01L24/02 ,  H01L24/05 ,  H01L24/29 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02215 ,  H01L2224/04105 ,  H01L2224/05147 ,  H01L2224/29187 ,  H01L2224/29188 ,  H01L2224/8012 ,  H01L2224/8312 ,  H01L2224/83896 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/0537 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/0549 ,  H01L2924/365 ,  H01L2224/80

Abstract: A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad, a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad, and a third barrier layer between portions of the first and second wafers where the first and second conductive pads are not bonded to each other.

公开(公告)号：US20130049225A1

公开(公告)日：2013-02-28

申请号：US13660177

申请日：2012-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-kyu KANG ,  Jung-Ho Kim ,  Jong-Wook Lee ,  Seung-woo Choi ,  Dae-Lok Bae

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/25 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.

Abstract translation: 微电子封装通过彼此堆叠集成电路制造。 每个集成电路包括具有微电子器件的半导体层和在半导体层上具有有选择性地互连微电子器件的布线的布线层。 在堆叠之后，形成延伸通过彼此堆叠的至少两个集成电路的通孔。 然后，通孔被选择性地电接触布线的导电材料填充。 还描述了相关微电子封装。