公开(公告)号：US20170358553A1

公开(公告)日：2017-12-14

申请号：US15413824

申请日：2017-01-24

Applicant: Samsung Electronics Co. Ltd.

Inventor： TAE-YEONG KIM ,  Pil-kyu KANG ,  Seok-ho KIM ,  Kwang-jin MOON ,  Ho-jin LEE

IPC: H01L23/00

CPC classification number: H01L24/94 ,  H01L24/02 ,  H01L24/05 ,  H01L24/29 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02215 ,  H01L2224/04105 ,  H01L2224/05147 ,  H01L2224/29187 ,  H01L2224/29188 ,  H01L2224/8012 ,  H01L2224/8312 ,  H01L2224/83896 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/0537 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/0549 ,  H01L2924/365 ,  H01L2224/80

Abstract: A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad, a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad, and a third barrier layer between portions of the first and second wafers where the first and second conductive pads are not bonded to each other.

公开(公告)号：US20170207158A1

公开(公告)日：2017-07-20

申请号：US15408977

申请日：2017-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil-kyu KANG ,  Ho-jin LEE ,  Byung-lyul PARK ,  Tae-yeong KIM ,  Seok-ho KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2224/16146 ,  H01L2225/06548

Abstract: A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on the first insulating layer, an intermediate device having an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer, an upper device having an upper substrate, a third insulating layer on the upper substrate, a second TSV bump on the third insulating layer, and a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad. An insulating first TSV spacer between the intermediate substrate and the TSV structure and an insulating second TSV spacer between the upper substrate and the TSV structure are spaced apart along a stacking direction.