公开(公告)号：US20200058609A1

公开(公告)日：2020-02-20

申请号：US16364775

申请日：2019-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi JIN ,  Ju-ll CHOI ,  Teahwa JEONG ,  Atsushi FUJISAKI

IPC: H01L23/00 ,  H01L21/768

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method includes providing a semiconductor substrate, forming a redistribution line on a top surface of the semiconductor substrate, and forming a passivation layer to cover the redistribution line on the top surface of the semiconductor substrate. The forming a redistribution line includes a first stage of forming a first segment of the redistribution line on the top surface of the semiconductor substrate, and a second stage of forming a second segment of the redistribution line on the first segment of the redistribution line. An average grain size of the second segment of the redistribution line is less than an average grain size of the first segment of the redistribution line.

公开(公告)号：US20200027784A1

公开(公告)日：2020-01-23

申请号：US16242122

申请日：2019-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-jeong PARK ,  Dong-chan LIM ,  Kwang-jin MOON ,  Ju-bin SEO ,  Ju-ll CHOI ,  Atsushi FUJISAKI

IPC: H01L21/768

Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.

公开(公告)号：US20210375725A1

公开(公告)日：2021-12-02

申请号：US17403154

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-ll CHOI ,  Kwang-Jin MOON ,  Byung-Lyul PARK ,  Jin-Ho AN ,  Atsushi FUJISAKI

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a preliminary via structure through a portion of a substrate; partially removing the substrate to expose a portion of the preliminary via structure; forming a protection layer structure on the substrate to cover the portion of the preliminary via structure that is exposed; partially etching the protection layer structure to form a protection layer pattern structure and to partially expose the preliminary via structure; wet etching the preliminary via structure to form a via structure; and forming a pad structure on the via structure to have a flat top surface.