公开(公告)号：US09786785B2

公开(公告)日：2017-10-10

申请号：US15083251

申请日：2016-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kook-Tae Kim ,  Young-Tak Kim ,  Ho-Sung Son ,  Seok-Jun Won ,  Ji-Hye Yi ,  Chul-Woong Lee

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/7851 ,  H01L29/41783 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.

公开(公告)号：US09312376B2

公开(公告)日：2016-04-12

申请号：US14155651

申请日：2014-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kook-Tae Kim ,  Young-Tak Kim ,  Ho-Sung Son ,  Seok-Jun Won ,  Ji-Hye Yi ,  Chul-Woong Lee

IPC: G11C11/34 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/41783 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.

Abstract translation: 提供半导体装置及其制造方法以及包括半导体装置的电子装置。 半导体器件包括形成在衬底上并包括沟槽的层间绝缘层，形成在沟槽中的栅电极，形成在栅电极的侧壁上以形成L形的第一栅极间隔件，形成在第二栅极间隔 所述第一栅极间隔物具有L形并且具有低于氮化硅的介电常数的介电常数，以及形成在所述第二栅极间隔物上的第三间隔物。

公开(公告)号：US11152415B2

公开(公告)日：2021-10-19

申请号：US16506074

申请日：2019-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Jin Lim ,  Kook-Tae Kim ,  Jong-Min Jeon ,  Jae-Sung Hur ,  Hye-Ri Hong

IPC: H01L27/146 ,  H04N5/369

Abstract: An image sensor includes a photoelectric converter in a pixel area of a substrate to generate photoelectrons in response to an incident light that is incident onto the pixel area, a signal generator on a first surface of the substrate in the pixel area to generate electric signals corresponding to image information of an object in accordance with the photoelectrons, and a pixel separation pattern penetrating through the substrate from the first surface of the substrate to a second surface of the substrate opposite to the first surface of the substrate, the pixel separation pattern including an insulation pattern having a refractive index smaller than that of the substrate and a metallic conductive pattern enclosed by the insulation pattern, and the pixel area being enclosed by the pixel separation pattern and isolated from a neighboring pixel area.

公开(公告)号：US10043806B2

公开(公告)日：2018-08-07

申请号：US15276274

申请日：2016-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kook-Tae Kim ,  Ho-Sung Son ,  Dong-Suk Shin ,  Hyun-Jun Sim ,  Ju-Ri Lee ,  Sung-Uk Jang

IPC: H01L29/15 ,  H01L31/0312 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L21/8238

Abstract: A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.

公开(公告)号：US10411011B2

公开(公告)日：2019-09-10

申请号：US16028080

申请日：2018-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kook-Tae Kim ,  Ho-Sung Son ,  Dong-Suk Shin ,  Hyun-Jun Sim ,  Ju-Ri Lee ,  Sung-Uk Jang

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/167 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L21/8238

Abstract: A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.