公开(公告)号：US20180309052A1

公开(公告)日：2018-10-25

申请号：US16018700

申请日：2018-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinhee HAN ,  Kiseok SUH ,  KyungTae NAM ,  Woojin KIM ,  Kwangil SHIN ,  Minkyoung JOO ,  Gwanhyeob KOH

IPC: H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A method of fabricating a magnetic memory device includes forming an interlayered insulating layer on a substrate, forming a landing pad to pass through the interlayered insulating layer, forming a protection insulating layer on the interlayered insulating layer to cover a top surface of the landing pad, forming a bottom electrode to pass through the protection insulating layer and through the interlayered insulating layer, forming a magnetic tunnel junction layer on the protection insulating layer; and patterning the magnetic tunnel junction layer to form a magnetic tunnel junction pattern on the bottom electrode.

公开(公告)号：US20140106535A1

公开(公告)日：2014-04-17

申请号：US14134008

申请日：2013-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyu LEE ,  Kiseok SUH ,  Tae Eung YOON

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1691 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1641

Abstract: A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.

Abstract translation: 存储器件包括半导体衬底中的下互连，下互连由不同于半导体衬底的材料制成，下互连上的选择元件以及选择元件上的存储元件。