公开(公告)号：US11031385B2

公开(公告)日：2021-06-08

申请号：US16725023

申请日：2019-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woo Seo ,  Jin Tae Kim ,  Tae Joong Song ,  Hyoung-Suk Oh ,  Keun Ho Lee ,  Dal Hee Lee ,  Sung We Cho

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/67 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H03K19/17736 ,  H03K19/17764 ,  H01L27/118 ,  H01L27/092 ,  H03K19/00 ,  H03K19/20 ,  H03K19/21

Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.

公开(公告)号：US09966446B2

公开(公告)日：2018-05-08

申请号：US15353163

申请日：2016-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Hee Park ,  Young Seok Song ,  Young Chul Hwang ,  Ui Hui Kwon ,  Keun Ho Lee ,  Jee Soo Chang ,  Jae Hee Choi

IPC: H01L29/76 ,  H01L29/417 ,  H01L29/78 ,  H01L23/532 ,  H01L23/522 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L23/5226 ,  H01L23/5329 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7851

Abstract: There is provided a semiconductor device to enhance operating characteristics by reducing parasitic capacitance between a gate electrode and other nodes. The semiconductor device includes: a substrate including an active region, and a field region directly adjacent to the active region; a first fin-type pattern protruding from the substrate in the active region; a first gate electrode disposed on the substrate, intersecting with the first fin-type pattern and including a first portion and a second portion, the first portion intersecting with the first fin-type pattern; a second gate electrode disposed on the substrate, intersecting with the first fin-type pattern and including a third portion and a fourth portion, the fourth portion facing the second portion, and the third portion intersecting with the first fin-type pattern and facing the first portion; a first interlayer insulating structure disposed between the first portion and the third portion, being on the substrate, and having a first dielectric constant; and a second interlayer insulating structure disposed between the second portion and the fourth portion, being on the substrate, and having a second dielectric constant which is different from the first dielectric constant.

公开(公告)号：US10553574B2

公开(公告)日：2020-02-04

申请号：US15298586

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woo Seo ,  Jin Tae Kim ,  Tae Joong Song ,  Hyoung-Suk Oh ,  Keun Ho Lee ,  Dal Hee Lee ,  Sung We Cho

IPC: H01L27/02 ,  H01L21/8234 ,  H01L23/528 ,  H01L21/67 ,  H01L23/522 ,  H01L27/088 ,  H03K19/177 ,  H03K19/00 ,  H03K19/20 ,  H03K19/21

Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.