公开(公告)号：US20250132203A1

公开(公告)日：2025-04-24

申请号：US18758118

申请日：2024-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Song Yi BAEK ,  Geumbi MUN ,  Junga LEE ,  Okran KIM ,  Seyoung HWANG ,  Kyoungchul SHIN ,  Sungsoo YANG ,  Daekwang WOO

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213

Abstract: A method for manufacturing a semiconductor device. The method may include forming an insulating interlayer on a substrate, forming tungsten patterns inside and on the insulating interlayer, forming an insulation pattern on the insulating interlayer to fill a space between the tungsten patterns, and the insulation pattern having a lowest point of an upper surface lower than an upper surface of each of the tungsten patterns, forming a preliminary tungsten oxide layer on the upper surface of each of the tungsten patterns, performing a first surface plasma treatment on the preliminary tungsten oxide layer to remove at least a portion of the preliminary tungsten oxide layer to form a tungsten oxide layer and a protective layer on the tungsten oxide layer, and forming an etch stop layer on the protective layer and the insulation pattern.

公开(公告)号：US20250022866A1

公开(公告)日：2025-01-16

申请号：US18409931

申请日：2024-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyeon JEONG ,  Hyunki KIM ,  Junga LEE

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a substrate, a passive element on the substrate, and a connection terminal connecting the substrate to the passive element. The substrate includes a base portion comprising an element pad connected to the connection terminal, and an upper insulating layer on the base portion to expose at least a portion of the base portion. The passive element is in contact with the upper insulating layer, and a thickness of the connection terminal and a thickness of the upper insulating layer are equal to each other.

公开(公告)号：US20240047411A1

公开(公告)日：2024-02-08

申请号：US18127513

申请日：2023-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junga LEE ,  Youngja KIM ,  Hyunki KIM ,  Youngmin LEE

IPC: H01L23/00 ,  B23K1/015 ,  B23K1/00 ,  B23K3/047

CPC classification number: H01L24/75 ,  B23K1/015 ,  B23K1/0016 ,  B23K3/047 ,  B23K2101/40

Abstract: An apparatus includes: a vapor generating chamber configured to accommodate a heat transfer fluid and to be filled with saturated vapor generated by the heat transfer fluid; a heater configured to heat the heat transfer fluid in the vapor generating chamber; a substrate stage configured to be movable upward or downward in the vapor generating chamber and to support a substrate on which an electronic device is mounted via a solder. The apparatus also includes at least one mesh plate extending in a horizontal direction in the vapor generating chamber. The at least one mesh plate includes a plurality of openings through which the vapor moves.

公开(公告)号：US20230141135A1

公开(公告)日：2023-05-11

申请号：US17977013

申请日：2022-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junga LEE ,  Yeonsook KIM ,  Wooseung JUNG

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/15

CPC classification number: H01L29/7843 ,  H01L27/10805 ,  H01L29/155

Abstract: An epitaxial wafer and a semiconductor memory device, the epitaxial wafer including a semiconductor substrate having a front surface and a rear surface opposite to each other; a strain relaxed buffer (SRB) layer on and entirely covering the front surface of the semiconductor substrate; and a multi-stack on and entirely covering a surface of the SRB layer, wherein the SRB layer includes a silicon germanium (SiGe) epitaxial layer including germanium (Ge) at a first concentration of about 2.5 at % to about 18 at %, and the multi-stack has a superlattice structure in which a plurality of silicon (Si) layers and a plurality of SiGe layers are alternately provided.

公开(公告)号：US20220093519A1

公开(公告)日：2022-03-24

申请号：US17306290

申请日：2021-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho PARK ,  Seunghwan KIM ,  Junyoung OH ,  Yonghyun KIM ,  Yongkwan LEE ,  Junga LEE

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L23/31

Abstract: A semiconductor package includes a first package substrate; a first semiconductor chip on the first package substrate; a first conductive connector on the first package substrate; and an interposer including a central portion on the first semiconductor chip and an outer portion having the first conductive connector attached thereto. The central portion of the interposer includes a bottom surface defining a recess from a bottom surface of the outer portion of the interposer in a vertical direction that is perpendicular to a top surface of the first package substrate. A thickness in the vertical direction of the outer portion of the interposer is greater than a thickness in the vertical direction of the central portion of the interposer.