公开(公告)号：US20210151089A1

公开(公告)日：2021-05-20

申请号：US17159516

申请日：2021-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-june Park ,  Jeong-don Ihm ,  Byung-hoon Jeong ,  Eun-ji Kim ,  Ji-yeon Shin ,  Young-don Choi

IPC: G11C7/22 ,  G11C16/32 ,  G11C7/10

Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.

公开(公告)号：US10937474B2

公开(公告)日：2021-03-02

申请号：US16668685

申请日：2019-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-june Park ,  Jeong-don Ihm ,  Byung-hoon Jeong ,  Eun-ji Kim ,  Ji-yeon Shin ,  Young-don Choi

IPC: G11C7/22 ,  G11C16/32 ,  G11C7/10 ,  G11C16/26 ,  H03K3/017 ,  H03K5/156

Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.

公开(公告)号：US20200066317A1

公开(公告)日：2020-02-27

申请号：US16668685

申请日：2019-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-june Park ,  Jeong-don Ihm ,  Byung-hoon Jeong ,  Eun-ji Kim ,  Ji-yeon Shin ,  Young-don Choi

IPC: G11C7/22 ,  G11C7/10 ,  G11C16/32

Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.

公开(公告)号：US10482935B2

公开(公告)日：2019-11-19

申请号：US15982431

申请日：2018-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-june Park ,  Jeong-Don Ihm ,  Byung-hoon Jeong ,  Eun-ji Kim ,  Ji-yeon Shin ,  Young-don Choi

IPC: G11C7/22 ,  G11C16/32 ,  G11C7/10 ,  G11C16/26 ,  H03K3/017 ,  H03K5/156

Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.

公开(公告)号：US11257531B2

公开(公告)日：2022-02-22

申请号：US17159516

申请日：2021-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-june Park ,  Jeong-don Ihm ,  Byung-hoon Jeong ,  Eun-ji Kim ,  Ji-yeon Shin ,  Young-don Choi

IPC: G11C7/22 ,  G11C16/32 ,  G11C7/10 ,  G11C16/26 ,  H03K3/017 ,  H03K5/156

Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.

公开(公告)号：US11114171B2

公开(公告)日：2021-09-07

申请号：US17010100

申请日：2020-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-yeon Shin ,  Jeong-don Ihm ,  Byung-hoon Jeong ,  Jung-june Park

IPC: G11C16/30 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  G11C7/10 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/26 ,  H01L27/1157

Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.

公开(公告)号：US10770149B2

公开(公告)日：2020-09-08

申请号：US16048786

申请日：2018-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-yeon Shin ,  Jeong-don Ihm ,  Byung-hoon Jeong ,  Jung-june Park

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/30 ,  G11C16/32

Abstract: A non-volatile memory device includes an output driver to output a data signal. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.