公开(公告)号：US20210036012A1

公开(公告)日：2021-02-04

申请号：US16848035

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio KIM ,  Yujin KIM ,  Philouk NAM ,  Youngseon SON ,  Kyongwon AN ,  Jumi YUN ,  Woojin JANG

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157 ,  H01L21/02

Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.

公开(公告)号：US20240315039A1

公开(公告)日：2024-09-19

申请号：US18483331

申请日：2023-10-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeongsik EOM ,  Inho KIM ,  Chankyu KIM ,  Jumi YUN ,  Young-Ho LEE ,  Dasom JUNG ,  Wongi HONG

IPC: H10B43/40 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/40 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a cell area, wherein the cell area includes: a cell array area; a connection area; a gate stacking structure including a plurality of gate electrodes, wherein the gate stacking structure includes an upper structure and a lower structure; a plurality of channel structures that penetrates the gate stacking structure in the cell array area; and a plurality of gate contact portions that penetrates the gate stacking structure in the connection area, wherein a bottom gate electrode in the cell array area is in a bottom portion of the upper structure and is adjacent to a channel structure among the plurality of channel structures, and wherein a bottom insulating portion in the connection area is in the bottom portion of the upper structure and is adjacent to a gate contact portion among the plurality of gate contact portions.

公开(公告)号：US20220238555A1

公开(公告)日：2022-07-28

申请号：US17722736

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio KIM ,  Yujin KIM ,  Philouk NAM ,  Youngseon SON ,  Kyongwon AN ,  Jumi YUN ,  Woojin JANG

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/02 ,  H01L27/1157 ,  H01L21/28

Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.