公开(公告)号：US20230300984A1

公开(公告)日：2023-09-21

申请号：US17939546

申请日：2022-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjin LEE ,  Jonghoon KIM ,  Kyoungsun KIM ,  Sungjoo PARK ,  Jinseong YUN ,  Young-Ho LEE ,  Jeonghyeon CHO ,  Heejin CHO

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/40

CPC classification number: H05K1/116 ,  H05K1/0298 ,  H05K3/4038 ,  H05K2201/09627

Abstract: An electronic device includes: a multilayered base substrate including a plurality of substrate bases stacked on each other; a first conductive via and a second conductive via penetrating the substrate bases and spaced from each other; a conductive line electrically connecting the first conductive via and the second conductive via to each other and disposed on at least one of the substrate bases of the plurality of substrate bases; and an open stub including a first end and a second end, wherein the first end is connected to a connector of the conductive line, and the second end is opened.

公开(公告)号：US20170040254A1

公开(公告)日：2017-02-09

申请号：US15331224

申请日：2016-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Young-Ho LEE ,  Seong-Soon CHO ,  Woon-Kyung LEE

IPC: H01L23/528 ,  H01L27/115

Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.

Abstract translation: 垂直型半导体器件中的阶形形状焊盘结构和布线结构包括具有第一线形状并且在边缘部分的上表面处包括第一焊盘区域的第一导电线和具有第二线形并且间隔开的第二导线 并且设置在第一导线上。 第一导线的端部延伸到第一位置。 第二焊盘区域包括在第二导线的边缘部分的上表面上。 第二导线的端部延伸到第一位置。 第二导线包括在垂直方向上与第一焊盘区域相对的部分处的凹部，以露出第一焊盘区域。 衬垫结构可以用在垂直型非易失性存储器件中。

公开(公告)号：US20200186474A1

公开(公告)日：2020-06-11

申请号：US16618617

申请日：2018-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Madhan Raj KANAGARATHINAM ,  Young-Ho LEE ,  Giri Venkata Prasad REDDY ,  Wang-Keun OH

IPC: H04L12/801 ,  H04L12/833 ,  H04L12/26 ,  H04L29/06

Abstract: Embodiments herein disclose methods and systems for accounting for MPTCP data usage. The embodiments include tracking MPTCP data usage of a plurality of applications. The embodiments include reporting the MPTCP data usage information to a data tracking module. Each of the plurality of applications is associated with a UID, which is tagged with MPTCP packets of the plurality of applications. The MPTCP packets of the plurality of applications can be transferred through at least one sub-socket, in at least one sub-flow. The at least one sub-flow can be associated with the system (OS) ID. The embodiments include updating the system UID, associated with the at least one sub-flow, with UIDs of the applications, whose data is included in the at least one sub-flow.

公开(公告)号：US20150078055A1

公开(公告)日：2015-03-19

申请号：US14325867

申请日：2014-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Hyun SEOK ,  Dohyung KIM ,  Kwangseop KIM ,  Young-Ho LEE

IPC: G11C11/401

CPC classification number: G11C11/401 ,  G11C5/025 ,  G11C5/04

Abstract: A memory module includes a printed circuit board; first memory chips disposed in parallel with a long axis of the printed circuit board along a first column; second memory chips disposed in parallel with the long axis of the printed circuit board along a second column; and passive elements disposed between the first memory chips and the second memory chips, wherein the passive elements are connected between input/output pins of each of the first and second memory chips and tap pins.

Abstract translation: 存储模块包括印刷电路板; 第一存储器芯片，沿着第一列与印刷电路板的长轴平行设置; 第二存储器芯片沿着第二列与印刷电路板的长轴平行布置; 以及设置在所述第一存储器芯片和所述第二存储器芯片之间的无源元件，其中所述无源元件连接在所述第一存储器芯片和所述第二存储器芯片中的每一个的输入/输出引脚之间。

公开(公告)号：US20240315039A1

公开(公告)日：2024-09-19

申请号：US18483331

申请日：2023-10-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeongsik EOM ,  Inho KIM ,  Chankyu KIM ,  Jumi YUN ,  Young-Ho LEE ,  Dasom JUNG ,  Wongi HONG

IPC: H10B43/40 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/40 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a cell area, wherein the cell area includes: a cell array area; a connection area; a gate stacking structure including a plurality of gate electrodes, wherein the gate stacking structure includes an upper structure and a lower structure; a plurality of channel structures that penetrates the gate stacking structure in the cell array area; and a plurality of gate contact portions that penetrates the gate stacking structure in the connection area, wherein a bottom gate electrode in the cell array area is in a bottom portion of the upper structure and is adjacent to a channel structure among the plurality of channel structures, and wherein a bottom insulating portion in the connection area is in the bottom portion of the upper structure and is adjacent to a gate contact portion among the plurality of gate contact portions.

公开(公告)号：US20140138759A1

公开(公告)日：2014-05-22

申请号：US14149884

申请日：2014-01-08

Applicant: SAMSUNG Electronics Co., Ltd.

Inventor： Young-Ho LEE ,  Keon-Soo KIM ,  Seong-Soon CHO ,  Jin- Hyun SHIN

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  H01L27/11531 ,  H01L28/20

Abstract: In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.

Abstract translation: 在集成电路器件及其制造方法中，电阻器图案位于衬底的器件隔离层上。 电阻器图案包括位于器件隔离层的凹部中的电阻体，以及与电阻体接触并连接在凹部的周围的器件隔离层上的连接器。 连接器具有在上部具有低于电阻体的电阻的金属硅化物图案。 栅极图案位于衬底的有源区上，并且在上部包括金属硅化物图案。 提供电阻器互连以与电阻器图案的连接器接触。 连接器和电阻器互连之间的接触电阻降低。