公开(公告)号：US20240400398A1

公开(公告)日：2024-12-05

申请号：US18680657

申请日：2024-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungbeom PARK ,  Samjong Choi ,  Sungbae Kim ,  Jongsoo Kim ,  Joonyoung Choi

IPC: C01B33/037 ,  C01B32/984 ,  C02F1/44 ,  C02F11/122 ,  C02F101/10 ,  C02F103/34 ,  H01L29/16 ,  H01M4/02 ,  H01M4/587

Abstract: A method of recycling silicon wastewater includes forming a silicon slurry from the silicon wastewater using a micro filtration device, forming a silicone cake from the silicon slurry using a filter press, and forming a silicon powder by drying the silicone cake in a reducing atmospheric.

公开(公告)号：US20220115504A1

公开(公告)日：2022-04-14

申请号：US17488825

申请日：2021-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyoung Choi

IPC: H01L29/40

Abstract: An integrated circuit device includes a substrate having an active area therein, a bit line on the substrate, and a direct contact, which extends between the active area and the bit line and electrically couples the bit line to a portion of the active area. A spacer structure is also provided, which extends on sidewalls of the bit line and on sidewalls of the direct contact. A field passivation layer is provided, which extends between the sidewalls of the direct contact and the spacer structure. The spacer structure and the field passivation layer may include different materials, and the field passivation layer may directly contact the sidewalls of the direct contact. The field passivation layer can include nonstoichiometric silicon oxide SiOx, where 0.04≤x≤0.4, and may have a thickness of less than about 25 Å.

公开(公告)号：US11888038B2

公开(公告)日：2024-01-30

申请号：US17488825

申请日：2021-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyoung Choi

IPC: H01L29/40

CPC classification number: H01L29/408

Abstract: An integrated circuit device includes a substrate having an active area therein, a bit line on the substrate, and a direct contact, which extends between the active area and the bit line and electrically couples the bit line to a portion of the active area. A spacer structure is also provided, which extends on sidewalls of the bit line and on sidewalls of the direct contact. A field passivation layer is provided, which extends between the sidewalls of the direct contact and the spacer structure. The spacer structure and the field passivation layer may include different materials, and the field passivation layer may directly contact the sidewalls of the direct contact. The field passivation layer can include nonstoichiometric silicon oxide SiOx, where 0.04≤x≤0.4, and may have a thickness of less than about 25 Å.

公开(公告)号：US11171038B2

公开(公告)日：2021-11-09

申请号：US16744446

申请日：2020-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namho Jeon ,  Joonyoung Choi ,  Jiyoung Kim ,  Junsoo Kim ,  Dongsoo Woo

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/84 ,  H01L27/108

Abstract: A fabrication method of an integrated circuit semiconductor device includes: forming a plurality of low dielectric pattern apart from each other on a substrate, the plurality of low dielectric pattern having a lower dielectric constant than the substrate; after forming the low dielectric pattern, forming a flow layer to bury the low dielectric pattern on the substrate; forming an epitaxial layer on the flow layer; and forming a transistor in the substrate comprising the low dielectric pattern buried by the flow layer and in the epitaxial layer.