公开(公告)号：US11984520B2

公开(公告)日：2024-05-14

申请号：US17671697

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Insung Joe ,  Jonghwa Shin ,  Joonkyo Jung ,  Jong Uk Kim

IPC: H01L31/0232 ,  H01L31/102

CPC classification number: H01L31/02327 ,  H01L31/102

Abstract: A light sensing device includes a semiconductor layer including a distributed Bragg reflector including a first surface of the semiconductor layer, and a photoelectric conversion unit including a second surface of the semiconductor layer, and the distributed Bragg reflector has a plurality of holes each having, in a cross-sectional view, a width gradually changing from a first width to a second width according to a width change period; a first electrode in one region of the semiconductor layer; and a second electrode on the second surface of the semiconductor layer and having a reflective metal.

公开(公告)号：US11037988B2

公开(公告)日：2021-06-15

申请号：US16802976

申请日：2020-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Uk Kim ,  Jeong Hee Park ,  Seong Geon Park ,  Soon Oh Park ,  Jung Moo Lee

IPC: H01L27/24 ,  H01L45/00 ,  G11C7/18 ,  G11C13/00 ,  G11C8/14

Abstract: A semiconductor device includes a first memory cell, a second memory cell, a first capping film, and a second capping film. The first memory cell includes a first ovonic threshold switch (OTS) on a first phase change memory. The second memory cell includes a second OTS on a second phase change memory. The first capping film is on side surfaces of the first and second memory cells. The second capping film is on the first capping film and fills a space between the first and second memory cells.

公开(公告)号：US11856794B2

公开(公告)日：2023-12-26

申请号：US17364378

申请日：2021-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Sung Choi ,  Jong Uk Kim ,  Kwang Min Park ,  Zhe Wu ,  Ja Bin Lee ,  Jae Ho Jung

IPC: H10B63/00 ,  H10N70/00

CPC classification number: H10B63/24 ,  H10N70/841 ,  H10N70/8828

Abstract: A semiconductor memory device includes a first memory cell provided on a substrate, a second memory cell provided on the substrate and spaced apart from the first memory cell, a passivation layer extending along a side surface of the first memory cell and a side surface of the second memory cell, and a gap fill layer covering the passivation layer. Each of the first memory cell and the second memory cell includes a selection pattern having ovonic threshold switching characteristics, and a storage pattern provided on the selection pattern. The passivation layer includes a lower portion filling a space between the selection pattern of the first memory cell and the selection pattern of the second memory cell, and an upper portion extending along a side surface of the storage pattern of each of the first memory cell and the second memory cell.

公开(公告)号：US20220059615A1

公开(公告)日：2022-02-24

申请号：US17364378

申请日：2021-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Sung CHOI ,  Jong Uk Kim ,  Kwang Min Park ,  Zhe Wu ,  Ja Bin Lee ,  Jae Ho Jung

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor memory device includes a first memory cell provided on a substrate, a second memory cell provided on the substrate and spaced apart from the first memory cell, a passivation layer extending along a side surface of the first memory cell and a side surface of the second memory cell, and a gap fill layer covering the passivation layer. Each of the first memory cell and the second memory cell includes a selection pattern having ovonic threshold switching characteristics, and a storage pattern provided on the selection pattern. The passivation layer includes a lower portion filling a space between the selection pattern of the first memory cell and the selection pattern of the second memory cell, and an upper portion extending along a side surface of the storage pattern of each of the first memory cell and the second memory cell.