公开(公告)号：US20160246529A1

公开(公告)日：2016-08-25

申请号：US14959131

申请日：2015-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooram KIM ,  Jinhyuk KIM ,  MoonSang KWON

IPC: G06F3/06 ,  G11C16/16

CPC classification number: G11C16/16 ,  G11C16/10 ,  G11C16/22

Abstract: An operating method of a storage device including a nonvolatile memory device includes receiving a logical address and a write command for first data from an external device, determining whether the write command includes security properties, detecting whether second data written into the same logical address as the logical address exists according to a result of the determination, and writing the first data into a unit memory area in which the second is stored according to a result of the detection.

Abstract translation: 包括非易失性存储装置的存储装置的操作方法包括从外部装置接收第一数据的逻辑地址和写入命令，确定写入命令是否包括安全属性，检测是否写入与第一数据相同的逻辑地址的第二数据 根据确定的结果存在逻辑地址，并且根据检测结果将第一数据写入存储第二数据的单元存储区域中。

公开(公告)号：US20240381641A1

公开(公告)日：2024-11-14

申请号：US18435342

申请日：2024-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungeun PARK ,  Solmi KWAK ,  Jinhyuk KIM ,  Hyeongjin KIM ,  Jeongyong SUNG ,  Minsoo SHIN ,  Seungjun SHIN ,  Joongshik SHIN ,  Sunghee CHUNG ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

Abstract: A vertical memory device may include a common source plate on a substrate including a first region and a second region; gate pattern structures on the common source plate and extending from the first region to the second region, wherein the gate pattern structures include gate patterns and first insulation layers, and wherein the adjacent gate pattern structures are spaced apart from each other; first separation patterns filling first openings between the adjacent gate pattern structures on the first region; second separation patterns filling second openings between the adjacent gate pattern structures on the second region, wherein at least one of the second separation patterns is connected to at least one of the first separation patterns, and wherein the second separation pattern has a shape different from a shape of the first separation pattern; and channel structures passing through the gate pattern structures on the first region.

公开(公告)号：US20220115294A1

公开(公告)日：2022-04-14

申请号：US17331951

申请日：2021-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggil KIM ,  Jinhyuk KIM ,  Jung-Hwan KIM

IPC: H01L23/48 ,  H01L29/78 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065

Abstract: A semiconductor device and an electronic system, the device including a substrate including a cell array region and a connection region; a stack including electrodes vertically stacked on the substrate; a source conductive pattern on the cell array region and between the substrate and the stack; a dummy insulating pattern on the connection region and between the substrate and the stack; a conductive support pattern between the stack and the source conductive pattern and between the stack and the dummy insulating pattern; a plurality of first vertical structures on the cell array region and penetrating the electrode structure, the conductive support pattern, and the source structure; and a plurality of second vertical structures on the connection region and penetrating the electrode structure, the conductive support pattern, and the dummy insulating pattern.

公开(公告)号：US20220093630A1

公开(公告)日：2022-03-24

申请号：US17241232

申请日：2021-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beyounghyun KOH ,  Seungmin SONG ,  Joongshik SHIN ,  Yongjin KWON ,  Jinhyuk KIM ,  Hongik SON

IPC: H01L27/11575 ,  H01L23/535 ,  H01L23/00 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: A semiconductor device includes a substrate having cell array and extension regions, a gate electrode structure having gate electrodes stacked in a first direction, a channel through the gate electrode structure on the cell array region, a first division pattern extending in the second direction on the cell array and extension regions, the first division pattern being at opposite sides of the gate electrode structure in a third direction, an insulation pattern structure partially through the gate electrode structure on the extension region, a through via through the insulation pattern structure, and a support layer on the gate electrode structure and extending on the cell array and extension regions, the support layer contacting an upper sidewall of the first division pattern, and the support layer not contacting an upper surface of a portion of the first division pattern on the extension region adjacent to the insulation pattern structure.