公开(公告)号：US20170345710A1

公开(公告)日：2017-11-30

申请号：US15407628

申请日：2017-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-oh PARK ,  Sang-chul SHIN ,  Chang-hwan KIM ,  Ji-young KIM

IPC: H01L21/768 ,  H01L23/522 ,  G11C8/08 ,  G03F7/095 ,  G11C7/06 ,  G03F7/20 ,  H01L23/528 ,  H01L21/027

CPC classification number: H01L21/76816 ,  G03F7/0035 ,  G03F7/095 ,  G03F7/2022 ,  G03F7/2041 ,  G11C7/06 ,  G11C8/08 ,  H01L21/0274 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528

Abstract: A method of forming a pattern of a semiconductor device includes: forming a first mask pattern comprising first mask lines extending in a first direction in a cell region and second mask lines extending in the first direction in a first core region, the first mask pattern covering a second core region; forming, on the first mask pattern, a second mask pattern comprising third mask lines extending in a second direction in the cell region and fourth mask lines extending in the second direction in the second core region, the second mask pattern covering the first core region; and forming a third mask pattern by using the second mask pattern, the third mask pattern comprising island-type masks in the cell region, fifth mask lines extending in the first direction in the first core region, and sixth mask lines extending in the second direction in the second core region.

公开(公告)号：US20140252440A1

公开(公告)日：2014-09-11

申请号：US14175305

申请日：2014-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min PARK ,  Dae-ik KIM ,  Ji-young KIM ,  Nak-jin SON ,  Yoo-sang HWANG

IPC: H01L23/48 ,  H01L27/105

CPC classification number: H01L23/485 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/41791 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at least an insulating layer, and a conductive plug structure electrically connecting the conductive line to the target connection region, wherein the conductive plug includes a first conductive plug having a first side wall, a bottom surface contacting the target connection region of the substrate, and a second side wall facing the first side wall of the conductive line, and a second conductive plug between the conductive line and the first conductive plug. The second conductive plug contacts both the first side wall of the conductive line and the second side wall of the first conductive plug.

Abstract translation: 半导体器件包括具有目标连接区域的衬底; 导电线，其具有通过至少绝缘层与衬底间隔开的第一侧壁和将导电线电连接到目标连接区域的导电插塞结构，其中导电插塞包括第一导电插塞，第一导电插塞具有第一侧壁 ，与基板的目标连接区域接触的底表面和面对导电线的第一侧壁的第二侧壁，以及在导线和第一导电塞之间的第二导电塞。 第二导电插头接触导电线的第一侧壁和第一导电插塞的第二侧壁。