公开(公告)号：US20220359341A1

公开(公告)日：2022-11-10

申请号：US17537689

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Hwan KIM ,  Jae Choon KIM ,  Kyung Suk OH

IPC: H01L23/38 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/48 ,  H01L25/16 ,  H01L23/373

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip bumps between the first package substrate and the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, a molding member which covers the plurality of second semiconductor chips, on the first semiconductor chip, and a thermoelectric cooling layer attached onto a surface of the first semiconductor chip. The thermoelectric cooling layer includes a cooling material layer extending along the surface of the first semiconductor chip, a first electrode pattern which surrounds the plurality of first chip bumps from a planar viewpoint, in the cooling material layer, and a second electrode pattern which surrounds the first electrode pattern from the planar viewpoint, in the cooling material layer.

公开(公告)号：US20250062279A1

公开(公告)日：2025-02-20

申请号：US18594300

申请日：2024-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggu KANG ,  Jae Choon KIM ,  Sung-Ho MUN ,  Hwanjoo PARK

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L25/18

Abstract: Disclosed is a semiconductor package comprising an interposer, a first semiconductor die below the interposer, and a first dummy die, a second dummy die, and a second semiconductor die over the interposer. The first semiconductor die, the second semiconductor die, the first dummy die, and the second dummy die overlap the interposer. The first semiconductor die overlaps the second semiconductor die. The second semiconductor die is between the first dummy die and the second dummy die.

公开(公告)号：US20200161201A1

公开(公告)日：2020-05-21

申请号：US16752044

申请日：2020-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Hyun Park ,  Jae Choon KIM

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H04N5/225 ,  H01L27/146

Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.

公开(公告)号：US20250079338A1

公开(公告)日：2025-03-06

申请号：US18752055

申请日：2024-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggu KANG ,  Youngjoon KOH ,  Jae Choon KIM ,  Sung-Ho MUN ,  Hwanjoo PARK

IPC: H01L23/00 ,  H01L23/24 ,  H01L23/28 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

Abstract: A semiconductor package may comrpise a substrate, a chip structure on the substrate, a passive element structure in the substrate and including a passive element, and a stiffening structure at least partially overlapping the passive element structure. A top surface of the passive element may be below a top surface of the substrate.

公开(公告)号：US20190057918A1

公开(公告)日：2019-02-21

申请号：US15922478

申请日：2018-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Hyun PARK ,  Jae Choon KIM

IPC: H01L23/31 ,  H01L27/146 ,  H01L25/065 ,  H01L23/532 ,  H01L23/528 ,  H01L23/34 ,  H01L21/768 ,  H04N5/225

CPC classification number: H01L23/3114 ,  H01L21/76877 ,  H01L23/345 ,  H01L23/5283 ,  H01L23/5329 ,  H01L25/0657 ,  H01L27/14603 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H04N5/2253

Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.

公开(公告)号：US20240413038A1

公开(公告)日：2024-12-12

申请号：US18402558

申请日：2024-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwanjoo PARK ,  Jae Choon KIM ,  Sunggu KANG ,  Taehwan KIM

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10

Abstract: A stacked semiconductor package includes: a first semiconductor package that includes a first region and a second region and includes a semiconductor chip including a first element at the first region and a second element at the second region; a second semiconductor package on the first region of the first semiconductor package; and a member for heat dissipation at the second region of the first semiconductor package and overlapping at least a portion of the second element in a vertical direction perpendicular to an in-plane direction of the first semiconductor package.

公开(公告)号：US20230117865A1

公开(公告)日：2023-04-20

申请号：US17862459

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eungchang LEE ,  Bangweon LEE ,  Jae Choon KIM ,  Kyung Suk OH

IPC: H01L23/367 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package including a substrate and at least one semiconductor chip on the substrate may be provided. The substrate may include a body layer having a top surface and a bottom surface, a first thermal conductive plate on the top surface of the body layer, the first thermal conductive plate connected to a ground terminal of the semiconductor chip, and a thermal conductive via penetrating the body layer and being in contact with the first thermal conductive plate.

公开(公告)号：US20170185119A1

公开(公告)日：2017-06-29

申请号：US15459403

申请日：2017-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heungkyu KWON ,  Jae Choon KIM ,  Eunseok CHO ,  Jichul KIM

IPC: G06F1/20 ,  G01J5/10 ,  G05B15/02

CPC classification number: G06F1/206 ,  G01J5/10 ,  G05B15/02

Abstract: A surface temperature management method of mobile device is provided. The method includes sensing a temperature of an application processor in an operation mode of the mobile device; and controlling the application processor using the sensed temperature and a surface temperature management table to manage a surface temperature of a target part of the mobile device. The surface temperature management table includes information related to the temperature of the application processor corresponding to the surface temperature of the target part in the operation mode.

公开(公告)号：US20140184312A1

公开(公告)日：2014-07-03

申请号：US14196602

申请日：2014-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Choon KIM ,  Eunseok CHO ,  Mi-Na CHOI ,  Kyoungsei CHOI ,  Heejung HWANG ,  Seran BAE

IPC: G05F1/46

CPC classification number: G05F1/463 ,  H01L23/34 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L25/16 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00

Abstract: An example embodiment relates to a semiconductor device including a semiconductor package in which a semiconductor chip is mounted on the package substrate. The semiconductor package may include a temperature measurement device and a temperature control circuit. The temperature measurement device may measure a temperature of the semiconductor package. The temperature control circuit may change an operation speed of the semiconductor package on the basis of the temperature of the semiconductor package measured by the temperature measurement device.

Abstract translation: 示例性实施例涉及一种包括半导体封装的半导体器件，其中半导体芯片安装在封装衬底上。 半导体封装可以包括温度测量装置和温度控制电路。 温度测量装置可以测量半导体封装的温度。 温度控制电路可以基于由温度测量装置测量的半导体封装的温度来改变半导体封装的操作速度。

公开(公告)号：US20240047290A1

公开(公告)日：2024-02-08

申请号：US18184386

申请日：2023-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Gu KANG ,  Jae Choon KIM ,  Hwan Joo PARK ,  Sung-Ho MUN

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/10

CPC classification number: H01L23/3128 ,  H01L24/16 ,  H01L21/565 ,  H01L24/73 ,  H01L24/48 ,  H01L25/105 ,  H01L24/32 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1094 ,  H01L2225/1058 ,  H01L2224/48227 ,  H01L2924/3511 ,  H01L2224/32225

Abstract: A semiconductor package with improved thermal properties is provided. The semiconductor package includes a first package including a first die, an interposer on the first package and including a first area and a second area. A second package is on a top face of the interposer in the second area, and a thermal diffusion structure is on a top face of the interposer in the first area. The thermal diffusion structure is configured so that heat generated in the first die is discharged through the thermal diffusion structure.