公开(公告)号：US20200381547A1

公开(公告)日：2020-12-03

申请号：US16743206

申请日：2020-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGMIN SONG ,  JUNBEOM PARK ,  BONGSEOK SUH ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

公开(公告)号：US20240038634A1

公开(公告)日：2024-02-01

申请号：US18336477

申请日：2023-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINKYU KIM ,  YUNSUK NAM ,  GUKHEE KIM ,  JUNBEOM PARK ,  JAEHYUN AHN ,  DARONG OH ,  DONGICK LEE

IPC: H01L23/48 ,  H10B10/00 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H10B10/10

CPC classification number: H01L23/481 ,  H10B10/125 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/775 ,  H10B10/10

Abstract: A semiconductor device, includes: a substrate having a first region and a second region; a first device on the substrate, in the first region; a second device on the substrate, in the second region; a front side interconnection structure including a plurality of interconnection layers electrically connected to the first device and the second device, on a front side of the substrate; and a back side buried interconnection structure adjacently to a back side of the substrate opposing the front side. The back side buried interconnection structure includes a back side buried insulating layer in a trench recessed from a back side of the substrate toward the front side of the substrate, and a back side buried conductive layer in the back side buried insulating layer. The back side buried interconnection structure is located in the first region or the second region.

公开(公告)号：US20230290881A1

公开(公告)日：2023-09-14

申请号：US18321962

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGMIN SONG ,  JUNBEOM PARK ,  BONGSEOK SUH ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/42392 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

公开(公告)号：US20220093786A1

公开(公告)日：2022-03-24

申请号：US17545072

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGMIN SONG ,  JUNBEOM PARK ,  BONGSEOK SUH ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.