公开(公告)号：US20210257264A1

公开(公告)日：2021-08-19

申请号：US17246778

申请日：2021-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGMIN YOO ,  JUYOUN KIM ,  HYUNGJOO NA ,  BONGSEOK SUH ,  JOOHO JUNG ,  EUICHUL HWANG ,  SUNGMOON LEE

IPC: H01L21/8238 ,  H01L27/118 ,  H01L21/762

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

公开(公告)号：US20200381547A1

公开(公告)日：2020-12-03

申请号：US16743206

申请日：2020-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGMIN SONG ,  JUNBEOM PARK ,  BONGSEOK SUH ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

公开(公告)号：US20230290881A1

公开(公告)日：2023-09-14

申请号：US18321962

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGMIN SONG ,  JUNBEOM PARK ,  BONGSEOK SUH ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/42392 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

公开(公告)号：US20230253264A1

公开(公告)日：2023-08-10

申请号：US18300983

申请日：2023-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGMIN YOO ,  JUYOUN KIM ,  HYUNGJOO NA ,  BONGSEOK SUH ,  JOOHO JUNG ,  EUICHUL HWANG ,  SUNGMOON LEE

IPC: H01L21/8238 ,  H01L27/118 ,  H01L21/762

CPC classification number: H01L21/823878 ,  H01L27/11807 ,  H01L21/76224 ,  H01L2027/11861 ,  H01L2027/11829 ,  H01L2027/11816

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

公开(公告)号：US20220093786A1

公开(公告)日：2022-03-24

申请号：US17545072

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGMIN SONG ,  JUNBEOM PARK ,  BONGSEOK SUH ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.