公开(公告)号：US20240404955A1

公开(公告)日：2024-12-05

申请号：US18800320

申请日：2024-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunkyoung SEO ,  Taehwan Kim ,  Hyunjung Song ,  Hyoeun Kim ,  Wonil Lee ,  Sanguk Han

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/367

Abstract: A semiconductor package includes a redistribution structure, a lower semiconductor device arranged on the redistribution structure and including first through electrodes each having a first horizontal width, a connecting substrate arranged on the redistribution structure and spaced apart from the lower semiconductor device in a horizontal direction and including second through electrodes each having a second horizontal width greater than the first horizontal width, a first molding layer arranged on the redistribution structure and surrounding a side surface of the lower semiconductor device and a side surface of the connecting substrate, and an upper semiconductor device arranged on the lower semiconductor device and the connecting substrate, the upper semiconductor device electrically connected to the first and second through electrodes. A plane area of the upper semiconductor device is greater than a plane area of the lower semiconductor device, and the first horizontal width is about 1 μm to about 7 μm and the second horizontal width is about 10 μm to about 20 μm.

公开(公告)号：US20230066895A1

公开(公告)日：2023-03-02

申请号：US17856122

申请日：2022-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yukyung Park ,  Hyunjung Song ,  Eunkyoung Choi

IPC: H01F17/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/498 ,  H01L21/56

Abstract: An inductor includes a semiconductor substrate provided with a plurality of wiring levels including a first wiring level and a second wiring level, a straight conductive line, at the first wiring level of the semiconductor substrate, having a first end, a conductive coil of a spiral pattern, at the second wiring level over the first wiring level, having a second end, and a conductive via vertically connecting the first end of the straight conductive line to the second end of the conductive coil. When viewed in a plan view, a plurality of dummy patterns are arranged in a first area defined by an innermost turn of the spiral pattern.

公开(公告)号：US12272628B2

公开(公告)日：2025-04-08

申请号：US17673865

申请日：2022-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Seungbin Baek ,  Hyunjung Song ,  Sangmin Yong

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18

Abstract: Provided is a semiconductor package including a first wiring pad on a package substrate; a first wiring connection part on the first wiring pad and including a wiring solder layer; a second wiring pad on the package substrate; a second wiring connection part on the second wiring pad and including a conductor; an interposer substrate on the first wiring connection part and the second wiring connection part, wherein a first substrate connection part and a second substrate connection part respectively electrically connected to the first wiring connection part and the second wiring connection part are arranged on a rear surface of the interposer substrate; and semiconductor chips apart from each other in a two-dimensional manner on the interposer substrate, wherein each of the semiconductor chips is electrically connected to the interposer substrate via a chip connection pillar.

公开(公告)号：US12237241B2

公开(公告)日：2025-02-25

申请号：US17718662

申请日：2022-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanggyoo Jung ,  Seungbin Baek ,  Hyunjung Song ,  Jisun Yang

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes: a package substrate; an interposer disposed on the package substrate; a first semiconductor chip mounted on the interposer; a second semiconductor chip mounted on the interposer adjacent to the first semiconductor chip, the second semiconductor chip having an overhang portion that does not overlap the interposer in a vertical direction; a first underfill disposed between the package substrate and the interposer, the first underfill having a first extension portion extending from a side surface of the interposer; a second underfill disposed between the interposer and the second semiconductor chip, the second underfill having a second extension portion extending to an upper surface of the package substrate along at least a portion of the first extension portion of the first underfill, wherein the second extension portion protrudes from the overhang portion contact the upper surface of the package substrate.

公开(公告)号：US12087696B2

公开(公告)日：2024-09-10

申请号：US18095900

申请日：2023-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunkyoung Seo ,  Taehwan Kim ,  Hyunjung Song ,  Hyoeun Kim ,  Wonil Lee ,  Sanguk Han

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/367 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.

公开(公告)号：US11574873B2

公开(公告)日：2023-02-07

申请号：US17003639

申请日：2020-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunkyoung Seo ,  Taehwan Kim ,  Hyunjung Song ,  Hyoeun Kim ,  Wonil Lee ,  Sanguk Han

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.

公开(公告)号：US20220415772A1

公开(公告)日：2022-12-29

申请号：US17673865

申请日：2022-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Seungbin Baek ,  Hyunjung Song ,  Sangmin Yong

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00

Abstract: Provided is a semiconductor package including a first wiring pad on a package substrate; a first wiring connection part on the first wiring pad and including a wiring solder layer; a second wiring pad on the package substrate; a second wiring connection part on the second wiring pad and including a conductor; an interposer substrate on the first wiring connection part and the second wiring connection part, wherein a first substrate connection part and a second substrate connection part respectively electrically connected to the first wiring connection part and the second wiring connection part are arranged on a rear surface of the interposer substrate; and semiconductor chips apart from each other in a two-dimensional manner on the interposer substrate, wherein each of the semiconductor chips is electrically connected to the interposer substrate via a chip connection pillar.